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SA-BX500EB / SA-BX500EE / SA-BX500EG
13.8. D-Port, Headphone, Digital, Volume, Wireless Adapter, Fan Circuit
1
2
3
SCHEMATIC DIAGRAM - 24
A
D
D-PORT CIRCUIT
R5100
R5101
330K
220K
B
CNA610
1
DOCK_L
14
DPORT_GND
13
DOCK_R
12
DOCK_L IN
11
C
TO
DOCK_R IN
10
MAIN(CPU)
DPORT_DET1
9
CIRCUIT
DPORT_DET2
8
C
(CNB610)
DOCK5VGND
7
IN SCHEMATIC
DOCK5V
6
DIAGRAM - 16
DO_UART_IN
5
DO_UART_OUT
4
AD_CNTL
3
IPOD_DET
2
DOCK5V
1
14
D
G
HEADPHONE CIRCUIT
JK601
1
L601
J0JBC0000014
HEADPHONE
3
L602
J0JBC0000014
2
E
I
DIGITAL CIRCUIT
JK4401
G
L4401
0
2
COAXIAL
(CD)
L4402
0
F
1
JK4404
R4405
47
OUTPUT
1
GND
OPTICAL 3
2
(TV)
DIGITAL IN
VCC
3
G
JK4403
R4401
47
OUTPUT
1
OPTICAL 2
GND
2
(BD/DVD PLAYER)
VCC
3
JK4402
R4402
47
OUTPUT
1
H
OPTICAL 1
GND
(DVD RECORDER)
2
VCC
3
1
2
3
4
5
6
: +B SIGNAL LINE
: IPOD AUDIO SIGNAL LINE
601
TL
C698
0
602
TL
CN611
G1
1
BATT_GND
2
GND
3
(MIC_L)/RF_DETECT
4
RESERVE
5
D-
6
DOCK_L IN
7
DPORT_GND
8
DOCK_L OUT
9
VGND
10
D+
VIDEO
11
12
DO_UART_OUT
OPTION V.1
13
DOCK_R OUT
14
ANT/(MIC_GND)/ID_SET
15
DPORT_DET2
16
DOCK_R IN
17
DPORT_DET1
18
(MIC_VCC)/RF_MUTE
19
BATT2
20
DO_UART_IN
21
A/D CONT/RF_SEL
22
(MIC_R)/LINK
23
DOCK5V
24
VBUS
G2
: MAIN SIGNAL LINE
C603
1000P
ZJ601*
E
JWB502*
TO
3
HPOUT-R
PANEL CIRCUIT
L603
J0JBC0000014
2
AGND
(JWA502*)
1
HPOUT-L
IN SCHEMATIC
DIAGRAM - 20
: +B SIGNAL LINE
: AUDIO SIGNAL LINE
C4403
0.1
R4406
10K
IC4401
C4407
C0JBAB000685
0.1
INVERTER
1
1A
1Y
6
L4403
G1C1R0MA0061
2
GND
VCC
5
3
2A
2Y
4
C4410
0.1
R4407
10K
L4404
G1C1R0MA0061
4
5
6
7
8
9
K
VOLUME CIRCUIT
VR621
EVEKD2F3024B
VOLUME JOG
L
WIRELESS ADAPTER CIRCUIT
1
C
TO
MAIN(CPU)
CIRCUIT
(PB8005)
IN SCHEMATIC
DIAGRAM - 17
22
M
FAN CIRCUIT
PB4401
11
1
D+3.3V
CN5991
2
RX4(AUX)
FAN DC OUT
3
DGND
B
TO FAN
TO
FAN GND
4
RX3(STB)
DSP CIRCUIT
FAN LOCK
5
DGND
6
RX2(TV)
(CN3004)
IN SCHEMATIC
7
DGND
DIAGRAM - 7
8
RX1(COAX)
9
DGND
10
TX
11
DGND
1
SA-BX500EB/EE/EG
D-PORT / HEADPHONE / DIGITAL / VOLUME / WIRELESS ADAPTER / FAN CIRCUIT
7
8
9
108
10
11
12
JWB503*
1
1
VOL ENC1
TO
2
VOL ENC2
PANEL CIRCUIT
2
(JWA503*)
3
D_GND
IN SCHEMATIC
4
KEY_GND
R621
1K
DIAGRAM - 20
3
S621
5
KEY2
RETURN/-SETUP
S622
OK
S623
TUNER V
S624
TUNER
: +B SIGNAL LINE
CN6301
CN6302
LB6301
0
AGND
22
1
AGND
LB6302
0
CH3_L_OUT
21
2
CH3_L_OUT
LB6303
0
AGND
20
3
AGND
LB6304
0
CH3_R_OUT
19
4
CH3_R_OUT
LB6305
0
AGND
18
5
AGND
LB6306
0
CH1_L_OUT
17
6
CH1_L_OUT
LB6307
0
AGND
16
7
AGND
LB6308
0
CH1_R_OUT
15
8
CH1_R_OUT
LB6309
0
AGND
14
9
AGND
LB6310
0
CH2_L_OUT
13
10
CH2_L_OUT
LB6311
0
AGND
12
11
AGND
LB6312
0
TO DIGITAL TRANSMITTER
CH2_R_OUT
11
12
CH2_R_OUT
LB6313
0
+5V
10
13
+5V
LB6314
0
PGND
9
14
5V_GND
LB6315
0
WM_DET
8
15
WM_DET
LB6316
0
SD0
7
16
SD0
LB6317
0
SDI
6
17
SDI
LB6318
0
SCL
5
18
SCL
LB6319
0
SSB
4
19
SSB
LB6320
0
INT
3
20
INT
LB6321
0
SM0
2
21
SM0
LB6322
0
SM1
1
22
SM1
G6301
JW5993*
1
1
FAN DC OUT
2
2
FAN GND
3
3
FAN LOCK
R5991
C5991
QR5991
56K
1
B1GBCFJN0004
FAN LOCK DETECT
10
11
12
13
14
A
E
B
C
: MAIN SIGNAL LINE
D
E
F
N
TO
D-AMP A (4CH) CIRCUIT
(CN5501)
IN SCHEMATIC
G
DIAGRAM - 25
H
13
14
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