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BLOCK DIAGRAM - SCHEMA SYNOPTIQUE - BLOCKSCHALTBILD - SCHEMA A BLOCCHI - ESQUEMA DE BLOQUES
CVBSOUT_AV2_CTRL
CVBSOUT_AV1_CTRL
FE6233
MA_Tuner
'L'=YC
'H'=CVBS
I
2
C
0xC2H
cv
MM 1507
+
Mux/Drv
MM1511
CVBS_OUT
19
Scart 1
FULL
'L'=YC
SCART
'H'=CVBS
MM 1507
cv
+
Mux/Drv
MM1511
CVBS_OUT
19
Scart 2
HALF
SCART
CVBS
SVHS
FRONT CINCH
RGB+FB Scart1, AV1_CVBS/YC Scart1
AV2_CVBS/YC Scart2
FAV_CVBS/YC FAV
VGA_Right_Audio, VGA_Left_Audio
Comp_Right_Audio, Comp_Left_Audio
Audio Block
Card Reader_Right_Audio, Card Reader_Left_Audio
Diagram
2
I
C 0x80, 82, 9AH
LINE_O/P_L
LINE_O/P_R
Audio Cinch Output
EFC031E I/O Concept
EFC031-IFC130-IFC230
First issue 12/05
TEA6415C
MA_Tuner_CVBS
MA_TUNER_CVBS
Y
AV1_Y_OUT
CHR
AV1_CHR_OUT
AV1_CVBS_OUT
AV1_CVBS/Y_IN
AV1_CHR_IN
Y
AV2_Y_OUT
CHR
AV2_CHR_OUT
AV2_CVBS_OUT
AV2_CVBS/Y_IN
AV2_CHR_IN
FAV_CVBS/Y_IN
FAV_CHR_IN
I
2
C
0x06H
INTERBOARD
CONNECTION
Master_Mute
AUDIO_STBY
RESET_AUDIO
Comp_Right_Audio
VGA_Right_Audio
Comp_Left_Audio
VGA_Left_Audio
Comp IN
Master_Mute
AUDIO_STBY
RESET_AUDIO
CVBSOUT_AV1_CTRL
CVBSOUT_AV2_CTRL
RGB+FB
32.11
Scart1
MHz
Video
Decoder
I
2
C
AV1_CVBS/YC
0x40/
SAA7117A
Scart1
0x48H
AV2_CVBS/YC
Scart2
FAV_CVBS/YC
FAV
16-bits YCbCr/
24-bits RGB
H-port 8 bits
H+V+Clock
MA_Tuner_CVBS
I-port 8 bits
H+V+Clock
ADC
I
2
C
MST9883C
0x98/
0x99H
YPbPr_VGA_SEL
FSAV330
VGA_TX, VGA_RX
Mux
COMP_YPbPr
VGA_RGB
RS232
DRV
2kbit
VGA
EEPROM
2
I
C
0xA0H
Audio Jack
TV KB
IR
Flat Panel Display
5 channel
LVDS
signal
CH0
LCD/Plasma TV
Controller
PW118B
14.318
MHz
CH1
16bits data
32bits data
21bits address
12bits address
DDR Frame Buffer
4M x 32 Bits x 4 banks
Flash Memory
MT46V16M16-6T
MT46V16M16-6T
32Mbit
256Mbit
256Mbit
(166MHz)
(166MHz)
M29W320EB70N6
64kbit
EEPROM
2
I
C
0xA0
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