Asus Aaeon EPIC-CFS7-PUC User Manual
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Asus Aaeon EPIC-CFS7-PUC User Manual

Asus Aaeon EPIC-CFS7-PUC User Manual

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EPIC-CFS7-PUC
EPIC Board
User's Manual 1
Ed
st
Last Updated: May 6, 2021

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Summary of Contents for Asus Aaeon EPIC-CFS7-PUC

  • Page 1 EPIC-CFS7-PUC EPIC Board User’s Manual 1 Last Updated: May 6, 2021...
  • Page 2 Copyright Notice This document is copyrighted, 2021. All rights are reserved. The original manufacturer reserves the right to make improvements to the products described in this manual at any time without notice. No part of this manual may be reproduced, copied, translated, or transmitted in any form or by any means without the prior written permission of the original manufacturer.
  • Page 3 Acknowledgements All other product names or trademarks are properties of their respective owners. The publisher and writer of this document make no claim to ownership of these products, nor is any claim implied for products not specifically named in this section. Microsoft Windows is a registered trademark of Microsoft Corp.
  • Page 4 Packing List Before setting up your product, please make sure the following items have been shipped: Item Quantity EPIC-CFS7-PUC ⚫ Jumper Cap ⚫ Back plate for cooler ⚫ If any of these items are missing or damaged, please contact your distributor or sales representative immediately.
  • Page 5 About this Document This User’s Manual contains all the essential information, such as detailed descriptions and explanations on the product’s hardware and software features (if any), its specifications, dimensions, jumper/connector settings/definitions, and driver installation instructions (if any), to facilitate users in setting up their product. Users may refer to the product page at AAEON.com for the latest version of this document.
  • Page 6 Safety Precautions Please read the following safety instructions carefully. It is advised that you keep this manual for future references All cautions and warnings on the device should be noted. Make sure the power source matches the power rating of the device. Position the power cord so that people cannot step on it.
  • Page 7 If any of the following situations arises, please the contact our service personnel: Damaged power cord or plug Liquid intrusion to the device iii. Exposure to moisture Device is not working as expected or in a manner as described in this manual The device is dropped or damaged Any obvious signs of damage displayed on the device...
  • Page 8 FCC Statement This device complies with Part 15 FCC Rules. Operation is subject to the following two conditions: (1) this device may not cause harmful interference, and (2) this device must accept any interference received including interference that may cause undesired operation.
  • Page 9 China RoHS Requirements (CN) 产品中有毒有害物质或元素名称及含量 AAEON System QO4-381 Rev.A0 有毒有害物质或元素 部件名称 铅 汞 镉 六价铬 多溴联苯 多溴二苯 醚(PBDE) (Pb) (Hg) (Cd) (Cr(VI)) (PBB) 印刷电路板 × ○ ○ ○ ○ ○ 及其电子组件 外部信号 × ○ ○ ○ ○ ○ 连接器及线材 外壳 ○...
  • Page 10 China RoHS Requirement (EN) Hazardous and Toxic Materials List AAEON System QO4-381 Rev.A0 Hazardous or Toxic Materials or Elements Component Name PCB and Components Wires & Connectors for Ext.Connections Chassis CPU & RAM HDD Drive LCD Module Optical Drive Touch Control Module Battery This form is prepared in compliance with the provisions of SJ/T 11364.

  • Page 11: Table Of Contents

    Table of Contents Chapter 1 - Product Specifications..................1 Specifications ......................2 Chapter 2 – Hardware Information ..................4 Dimensions ....................... 5 Jumpers and Connectors ..................8 List of Jumpers (Main Board) ................11 2.3.1 Front Panel PIN Header (JP1) ..............11 2.3.2 AT/ATX mode Selection (JP2) ..............
  • Page 12 List of Jumpers (POE Board) ................26 2.5.1 OUT2 Select (JP1) ..................26 2.5.2 AGND2 Select (JP2) ................... 26 2.5.3 AGND1 Select (JP3) ..................26 2.5.4 OUT1 Select (JP4) ..................27 List of Connectors (POE Board) ................28 2.6.1 12V DC In (CN1) ..................28 2.6.2 LAN RJ-45 Port (CN2/CN3) ..............
  • Page 13 3.4.6 Digital IO Port Configuration ..............54 Setup Submenu: Chipset ..................55 3.5.1 System Agent (SA) Configuration ............56 3.5.2 PCH-IO Configuration ................57 Setup Submenu: Security ..................58 3.6.1 Secure Boot ....................59 3.6.1.1 Key Management ................. 60 Setup Submenu: Boot ..................62 3.7.1 BBS Priorities ....................

  • Page 14: Chapter 1 - Product Specifications

    Chapter 1 Chapter 1 - Product Specifications...

  • Page 15: Specifications

    Specifications System Form Factor 4” EPIC Board 8th Generation Intel® Core™ Processor family CPU Frequency Up to 4.6GHz Chipset Intel® H310/Q370 (TDP: 6W) Memory Type DDR4 2666 MHz SODIMM x 2 (Dual Channel, Non-ECC) Max. Memory Capacity Up to 32GB BIOS AMI UEFI Wake on LAN...
  • Page 16 Display VGA/LCD Controller 8th Generation Intel® Core™ Processor family Video Output HDMI x 2 Backlight Inverter Supply — Ethernet Intel® I211, 10/100/1000Base, RJ45 x 4 (Supports PoE 802.3af); two ports on main board, two ports on daughter board Audio — USB Port USB3.2 Gen 2/ USB2.0 x 4 (Rear I/O) USB2.0 x 2 (Internal header)

  • Page 17: Chapter 2 - Hardware Information

    Chapter 2 Chapter 2 – Hardware Information...

  • Page 18: Dimensions

    Dimensions System Chapter 2 – Hardware Information...
  • Page 19 Board Chapter 2 – Hardware Information...
  • Page 20 POE Carrier Board DIO Carrier Board Chapter 2 – Hardware Information...

  • Page 21: Jumpers And Connectors

    Jumpers and Connectors Chapter 2 – Hardware Information...
  • Page 22 Chapter 2 – Hardware Information...
  • Page 23 POE Carrier Board DIO Carrier Board Chapter 2 – Hardware Information...

  • Page 24: List Of Jumpers (Main Board)

    List of Jumpers (Main Board) Please refer to the table below for all of the board’s jumpers that you can configure for your application. Label Function Front Panel PIN Header AT/ATX Mode Selection Clear C-MOS PIN Header 2.3.1 Front Panel PIN Header (JP1) Signal Description Signal Description EXT_PWRBTN#...

  • Page 25: At/Atx Mode Selection (Jp2)

    2.3.2 AT/ATX mode Selection (JP2) ATX Mode AT mode (Default) 2.3.3 Clear CMOS Jumper (JP3) Normal (Default) Clear CMOS Chapter 2 – Hardware Information...

  • Page 26: List Of Connectors (Main Board)

    List of Connectors (Main Board) The table below lists all of the board’s connectors, configurable for your application. Label Function LPC Connector for Debug SATA Connector SATA Power Connector 2-Pin DC IN Connector DIO Power Connector PCIe [x4] FPC Connector CN10 CPU Fan Connector CN11...

  • Page 27: Lpc Port (Cn1)

    2.4.1 LPC Port (CN1) Signal Description Signal Description LPC_AD0 RST# LPC_AD1 LPC_AD2 LPC_AD3 I2C0_data/SMB_data P3V3 I2C0_CLK/SMB_CLK FRAME# INT_SERIRQ Chapter 2 – Hardware Information...

  • Page 28: Sata Connector (Cn2)

    2.4.2 SATA Connector (CN2) Signal Description Signal Description SATA_RXN0 SATA_TXP0 SATA_RXP0 SATA_TXN0 2.4.3 SATA Power (CN4) Signal Description +5V max 1A Chapter 2 – Hardware Information...

  • Page 29: Pin Dc In Connector (Cn5)

    2.4.4 2 Pin DC IN Connector (CN5) +VIN GND Signal Description +12V 2.4.5 DIO Power Connector (CN6) Signal Description +V5S max 0.5A +V3P3S max 1A Chapter 2 – Hardware Information...

  • Page 30: Pcie [X4] Fpc Connector (Cn9)

    2.4.6 PCIe [x4] FPC Connector (CN9) Signal Description Signal Description +V3P3S PCIE_12_TXN +V3P3S PCIE_12_TXP +V3P3S SMB_DATA PCIE_11_TXN SMB_CLK PCIE_11_TXP BUF_PLT_RST# +V3P3A PCIE_10_TXN PCIE_10_TXP PCIE_10_RXP PCIE_10_RXN PCIE_3_CLK_DN PCIE_3_CLK_DP PCIE_12_RXP PCIE_12_RXN PCIE_9_TXN PCIE_9_TXP PCIE_11_RXP PCIE_11_RXN +V12V +V12V PCIE_9_RXP +V12V PCIE_9_RXN +V12V +V12V Chapter 2 –...

  • Page 31: Cpu Fan Connector (Cn10)

    2.4.7 CPU FAN Connector (CN10) Signal Description Current FAN_POWER 1 Amp FAN_TAC FAN_CTL 2.4.8 POE LAN (RJ-45) Connector (CN11) Signal Description Signal Description LAN2_MDI0_N LAN2_LED_100# LAN2_MDI0_P LAN2_LED_1000# LAN2_MDI1_N AGND LAN2_MDI1_P OUT2_LED LAN2_MDI2_N LAN2_MDI2_P LAN2_MDI2_N LAN2_MDI3_P R11A OUT2 R10A R12A AGND LAN1_MDI0_N LAN1_LED_100# LAN1_MDI0_P...

  • Page 32: Rs232/422/485 Connector Com1, Com2 (Cn12/13)

    Signal Description Signal Description LAN1_MDI1_N AGND LAN1_MDI1_P OUT1_LED LAN1_MDI2_N LAN1_MDI2_P LAN1_MDI3_N LAN1_MDI3_P R11B OUT1 R10B R12B AGND 2.4.9 RS232/422/485 connector COM1, COM2 (CN12/13) RS232 Signal Description Signal Description DCD2 CTS2 DSR2 DTR2 RTS2 Chapter 2 – Hardware Information...
  • Page 33 RS422 Signal Description Signal Description RS422_TX2- RS422_RX2- RS422_TX2+ NC/+5V/+12V max 0.5A RS422_RX2+ RS485 Signal Description Signal Description RS485_ D2- RS485_D2+ NC/+5V/+12V max 0.5A Chapter 2 – Hardware Information...

  • Page 34: Hdmi Connector (Cn14/15)

    2.4.10 HDMI Connector (CN14/15) Signal Description Signal Description HDMI_TX2+ HDMI_CLK- HDMI_TX2- HDMI_TX1+ DDC_CLK HDMI_TX1- DDC_DATA HDMI_TX0+ HDMI_TX0- HDMI_HPD HDMI_CLK+ Chapter 2 – Hardware Information...

  • Page 35: Usb 3.2 Gen 2 Connector (Cn16)

    2.4.11 USB 3.2 Gen 2 Connector (CN16) Signal Description Signal Description +5VSB +5VSB USB1_D- USB2_D- USB1_D+ USB2_D+ USB1_SSRX− USB2_SSRX− USB1_SSRX+ USB2_SSRX+ USB1_SSTX− USB2_SSTX− USB1_SSTX+ USB2_SSTX+ Chapter 2 – Hardware Information...

  • Page 36: Usb 3.2 Gen 2 Connector (Cn17)

    2.4.12 USB 3.2 Gen 2 Connector (CN17) Signal Description Signal Description +5VSB +5VSB USB3_D- USB4_D- USB3_D+ USB4_D+ USB3_SSRX− USB4_SSRX− USB3_SSRX+ USB4_SSRX+ USB3_SSTX− USB4_SSTX− USB3_SSTX+ USB4_SSTX+ 2.4.13 RTC Connector (CN18) Signal Description RTCVCC Chapter 2 – Hardware Information...

  • Page 37: Usb 2.0 Connector (Cn19)

    2.4.14 USB 2.0 Connector (CN19) Signal Description Signal Description USBD- USBD- USBD+ USBD+ 2.4.15 Mini Card Connector (CN20) Signal Description Signal Description PCIE_WAKE# +3.3VSB +1.5V SMB_CLK PCIE_TX- +1.5V SMB_DATA PCIE_TX+ UIM_PWR UIM_DATA USB_D- PCIE_REF_CLK- Chapter 2 – Hardware Information...

  • Page 38: Ddr4 So-Dimm Slot (Dimm1 & Dimm2)

    Signal Description Signal Description UIM_CLK USB_D+ PCIE_REF_CLK+ +3.3VSB UIM_RST +3.3VSB UIM_VPP W_DISABLE# PCIE_RST# +1.5V PCIE_RX- +3.3VSB PCIE_RX+ +3.3VSB 2.4.16 DDR4 SO-DIMM Slot (DIMM1 & DIMM2) Standard specification Chapter 2 – Hardware Information...

  • Page 39: List Of Jumpers (Poe Board)

    List of Jumpers (POE Board) Label Function OUT2 Select AGND2 Select AGND1 Select OUT1 Select 2.5.1 OUT2 Select (JP1) OUT2_1236 (Default) OUT2_4578 2.5.2 AGND2 Select (JP2) AGND2_1236 (Default) AGND2_4578 2.5.3 AGND1 Select (JP3) AGND1_1236 (Default) AGND1_4578 Chapter 2 – Hardware Information...

  • Page 40: Out1 Select (Jp4)

    2.5.4 OUT1 Select (JP4) OUT1_1236 (Default) OUT1_4578 Chapter 2 – Hardware Information...

  • Page 41: List Of Connectors (Poe Board)

    List of Connectors (POE Board) Label Function 12V DC IN LAN2 RJ-45 Port LAN1 RJ-45 Port FPC Cable Port (Connect to EPIC-CFS7) 2.6.1 12V DC In (CN1) Pin Name Signal Type Signal Level +V_IN +V_IN 2.6.2 LAN RJ-45 Port (CN2/CN3) Pin Name Signal Type Signal Level...

  • Page 42: Fpc Cable Port (Cn4)

    Pin Name Signal Type Signal Level TRP3- DIFF TRP2- DIFF TRP4+ DIFF TRP4- DIFF 2.6.3 FPC Cable Port (CN4) Pin Name Signal Type Signal Level +V12S +12V +V12S +12V +V12S +12V +V12S +12V +V12S +12V PCIE_9_TXP DIFF PCIE_9_TXN DIFF Chapter 2 – Hardware Information...
  • Page 43 Pin Name Signal Type Signal Level PCIE_3_CLK_DP DIFF PCIE_3_CLK_DN DIFF PCIE_10_TXP DIFF PCIE_10_TXN DIFF PCIE_11_TXP DIFF PCIE_11_TXN DIFF PCIE_12_TXP DIFF PCIE_12_TXN DIFF PCIE_9_RXN DIFF PCIE_9_RXP DIFF PCIE_11_RXN DIFF PCIE_11_RXP DIFF PCIE_12_RXN DIFF PCIE_12_RXP DIFF PCIE_10_RXN DIFF PCIE_10_RXP DIFF +V3P3A DIFF +3.3V BUF_PLT_RST# +3.3V...
  • Page 44 Pin Name Signal Type Signal Level SMB_CLK +3.3V SMB_DATA +3.3V +V3P3S +3.3V +V3P3S +3.3V +V3P3S +3.3V Chapter 2 – Hardware Information...

  • Page 45: List Of Connectors (Dio Board)

    List of Connectors (DIO Board) Note: There are no jumpers on DIO Board. Label Function LPC Port Power In (from EPIC-CFS7) GPI Port GPO Port 2.7.1 LPC Port (CN1) Pin Name Signal Type Signal Level LPC_AD0 +3.3V LPC_AD1 +3.3V LPC_AD2 +3.3V LPC_AD3 +3.3V...

  • Page 46: Power In (Cn2)

    Pin Name Signal Type Signal Level BUF_PLT_RST# +3.3V CLK_LPC_25M_DBG SMB_DATA_3P3 +3.3V SMB_CLK_3P3 +3.3V SMB_ALERT#_3P# +3.3V 2.7.2 Power In (CN2) Pin Name Signal Type Signal Level +V5S +V3P3S +3.3V Chapter 2 – Hardware Information...

  • Page 47: Gpi Port (Cn3)

    2.7.3 GPI Port (CN3) Pin Name Signal Type Signal Level GPI0 +12V/+24V GPI1 +12V/+24V GPI2 +12V/+24V GPI3 +12V/+24V GPI4 +12V/+24V GPI5 +12V/+24V GPI6 +12V/+24V GPI7 +12V/+24V PC_VDD +12V/+24V GPI8 +12V/+24V GPI9 +12V/+24V GPI10 +12V/+24V GPI11 +12V/+24V Chapter 2 – Hardware Information...

  • Page 48: Gpo Port (Cn4)

    Pin Name Signal Type Signal Level GPI12 +12V/+24V GPI13 +12V/+24V GPI14 +12V/+24V GPI15 +12V/+24V PC_VDD +12V/+24V 2.7.4 GPO Port (CN4) Pin Name Signal Type Signal Level GPO0 +12V/+24V GPO1 +12V/+24V GPO2 +12V/+24V GPO3 +12V/+24V GPO4 +12V/+24V GPO5 +12V/+24V Chapter 2 – Hardware Information...
  • Page 49 Pin Name Signal Type Signal Level GPO6 +12V/+24V GPO7 +12V/+24V PC_GND GPO8 +12V/+24V GPO9 +12V/+24V GPO10 +12V/+24V GPO11 +12V/+24V GPO12 +12V/+24V GPO13 +12V/+24V GPO14 +12V/+24V GPO15 +12V/+24V PC_GND Chapter 2 – Hardware Information...

  • Page 50: Block Diagrams

    Block Diagrams Chapter 2 – Hardware Information...
  • Page 51 Chapter 2 – Hardware Information...

  • Page 52: Chapter 3 - Bios Setup

    Chapter 3 Chapter 3 - BIOS Setup...

  • Page 53: System Test And Initialization

    System Test and Initialization The EPIC-CFS7-PUC board uses certain routines to test and initialize board hardware. If the routines encounter an error during the tests, you will either hear a few short beeps or see an error message on the screen. There are two kinds of errors: fatal and non-fatal.

  • Page 54: Ami Bios Setup

    AMI BIOS Setup AMI BIOS ROM has a built-in Setup program that allows users to modify the basic system configuration. This information is stored in a battery-backed CMOS RAM and BIOS NVRAM so that it retains the Setup information when the power is turned off. To enter setup, power on the computer and press <Del>or <ESC>...

  • Page 55: Setup Submenu: Main

    Setup Submenu: Main Chapter 3 – BIOS Setup...

  • Page 56: Setup Submenu: Advanced

    Setup Submenu: Advanced Chapter 3 – BIOS Setup...

  • Page 57: Cpu Configuration

    3.4.1 CPU Configuration Options Summary Active Processor Cores Optimal Default, Failsafe Default Number of cores to enable in each processor package. Intel (VMX) Virtualization Disabled Technology Enabled Optimal Default, Failsafe Default When enabled, a VMM can utilize the additional hardware capabilities provided by Vanderpool Technology.

  • Page 58: Sata Configuration

    3.4.2 SATA Configuration Options Summary SATA Controller(s) Disabled Enabled Optimal Default, Failsafe Default Enable/Disable SATA Device. Port 0 Disabled Optimal Default, Failsafe Default Enabled Enable or Disable SATA Port mSATA port Disabled Enabled Optimal Default, Failsafe Default Enable or Disable SATA Port Chapter 3 –...

  • Page 59: Hardware Monitor

    3.4.3 Hardware Monitor Chapter 3 – BIOS Setup...

  • Page 60: Smart Fan Mode Configuration

    3.4.3.1 Smart Fan Mode Configuration Auto Duty-Cycle Mode Options Summary FAN1 Output Output PWM mode (open drain) Mode Linear Fan Application Output PWM mode (push pull) Optimal Default, Failsafe Default Output PWM mode (push pull) to control 4-wire fans. Linear fan application circuit to control 3-wire fan speed by fan’s power terminal. Output PWM mode (open drain) to control Intel 4-wire fans.
  • Page 61 Auto RPM Mode Options Summary RPM Percentage Auto fan speed control. Fan speed will follow different temperature by different RPM 1-100 Temperature Chapter 3 – BIOS Setup...
  • Page 62 Manual Duty Mode Options Summary Manual Duty Mode Optimal Default, Failsafe Default Manual mode fan control, user can write expected duty cycle (PWM fan type) 1-100 Chapter 3 – BIOS Setup...

  • Page 63: Sio Configuration

    3.4.4 SIO Configuration Chapter 3 – BIOS Setup...

  • Page 64: Serial Port 1 Configuration

    3.4.4.1 Serial Port 1 Configuration Options Summary Use This Device Disable Enable Optimal Default, Failsafe Default Enable or Disable this Logical Device. Possible: Use Automatic Settings Optimal Default, Failsafe Default IO=3F8h; IRQ=4 IO=2F8h; IRQ=3 Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts.

  • Page 65: Serial Port 2 Configuration

    3.4.4.2 Serial Port 2 Configuration Options Summary Use This Device Disable Enable Optimal Default, Failsafe Default Enable or Disable this Logical Device. Possible: Use Automatic Settings Optimal Default, Failsafe Default IO=2F8h; IRQ=3 IO=3F8h; IRQ=4 Allows user to change Device's Resource settings. New settings will be reflected on This Setup Page after System restarts.

  • Page 66: Power Management

    3.4.5 Power Management Options Summary Power Mode ATX Type Optimal Default, Failsafe Default AT Type Select system power mode Restore AC Power Last State Optimal Default, Failsafe Default Loss Always On Always Off IO Restore AC power Loss RTC wake system from Disable Optimal Default, Failsafe Default Fixed Time...

  • Page 67: Digital Io Port Configuration

    3.4.6 Digital IO Port Configuration Options Summary DIO Port* Output Input Set DIO as Input or Output Output Level High Optimal Default, Failsafe Default Set output level when DIO pin is output Chapter 3 – BIOS Setup...

  • Page 68: Setup Submenu: Chipset

    Setup Submenu: Chipset Chapter 3 – BIOS Setup...

  • Page 69: System Agent (Sa) Configuration

    3.5.1 System Agent (SA) Configuration Chapter 3 – BIOS Setup...

  • Page 70: Pch-Io Configuration

    3.5.2 PCH-IO Configuration Options Summary HD Audio Disabled Enabled Optimal Default, Failsafe Default Control Detection of the HD-Audio device. Disabled = HDA will be unconditionally disabled Enabled = HDA will be unconditionally enabled. MiniCard Slot Function SATA Optimal Default, Failsafe Default PCIe Select function enabled for Half-MiniCard (CN20) slot Chapter 3 –...

  • Page 71: Setup Submenu: Security

    Setup Submenu: Security Change User/Administrator Password You can set an Administrator Password or User Password. An Administrator Password must be set before you can set a User Password. The password will be required during boot up, or when the user enters the Setup utility. A User Password does not provide access to many of the features in the Setup utility.

  • Page 72: Secure Boot

    3.6.1 Secure Boot Options Summary Secure Boot Disabled Optimal Default, Failsafe Default Enabled Secure Boot feature is Active if Secure Boot is Enabled, Platform Key(PK) is enrolled and the System is in User mode. The mode change requires platform reset Secure Boot Mode Custom Optimal Default, Failsafe Default...

  • Page 73: Key Management

    3.6.1.1 Key Management Options Summary Factory Key Provision Disabled Optimal Default, Failsafe Default Enabled Secure Boot feature is Active if Secure Boot is Enabled, Platform Key(PK) is enrolled and the System is in User mode. The mode change requires platform reset Restore Factory Keys Force System to User Mode.
  • Page 74 Options Summary Restore DB defaults Restore DB variable to factory defaults Platform Key(PK) Details Export Update Delete Key Exchange Keys Details Export Update Append Delete Authorized Signatures Details Export Update Append Delete Forbidden Signatures Details Export Update Append Delete Authorized TimeStamps Update Append OsRecovery Signatures...

  • Page 75: Setup Submenu: Boot

    Setup Submenu: Boot Options Summary Quiet Boot Disabled Enabled Optimal Default, Failsafe Default Enable or disable showing boot logo. Lunch PXE ROM Disabled Optimal Default, Failsafe Default Enabled Controls the execution of UEFI and Legacy Network OpROM Chapter 3 – BIOS Setup...

  • Page 76: Bbs Priorities

    3.7.1 BBS Priorities Chapter 3 – BIOS Setup...

  • Page 77: Setup Submenu: Save & Exit

    Setup Submenu: Save & Exit Chapter 3 – BIOS Setup...

  • Page 78: Chapter 4 - Driver Installation

    Chapter 4 Chapter 4 – Driver Installation...

  • Page 79: Driver Installation

    Driver Installation Drivers for the EPIC-CFS7-PUC can be downloaded from the product page on the AAEON website by following this link: https://www.aaeon.com/en/p/epic-boards-epic-CFS7-PUC Download the driver(s) you need and follow the steps below to install them. Before beginning installation, use the following chart to determine if your operating system (OS) is compatible with the drivers AAEON provides for the EPIC-CFS7-PUC.
  • Page 80 Step 2 – Install Graphics Drivers Open the Step 2 - Graphic folder Open the win64_25.20.100.6373.exe file in the folder Follow the instructions Drivers will be installed automatically Step 3 – Install Network Drivers Open the Step 3 – Network folder Open the ProWinx64.exe file in the folder Follow the instructions Drivers will be installed automatically...

  • Page 81: Appendix A - I/O Information

    Appendix A Appendix A - I/O Information...

  • Page 82: I/O Address Map

    I/O Address Map Appendix A – I/O Information...
  • Page 83 Appendix A – I/O Information...
  • Page 84 Appendix A – I/O Information...

  • Page 85: Memory Address Map

    Memory Address Map Appendix A – I/O Information...

  • Page 86: Irq Mapping Chart

    IRQ Mapping Chart Appendix A – I/O Information...
  • Page 87 Appendix A – I/O Information...

  • Page 88: Appendix B - Watchdog Timer Programming

    Appendix B Appendix B - Watchdog Timer Programming...

  • Page 89: Watchdog Timer Registers

    Watchdog Timer Registers Table 1 : Watch dog relative IO address Default Value Note I/O Base I/O Base address for Watchdog operation. 0x2E Address This address is assigned by SIO LDN7 Table 2 : Watchdog relative register table Register Offset BitNum Value Note...

  • Page 90: Watchdog Sample Program

    Watchdog Sample Program ****************************************************************************** // WDT I/O operation relative definition (Please reference to Table 1) #define WDTAddr 0x510 // WDT I/O base address Void WDTWriteByte(byte Register, byte Value); byte WDTReadByte(byte Register); Void WDTSetReg(byte Register, byte Bit, byte Val); // Watch Dog relative definition (Please reference to Table 2) #define DevReg 0x00 // Device configuration register #define WDTRstBit 0x80 // Watchdog WDTRST# (Bit7)
  • Page 91 ******************************************************************************* // Procedure : AaeonWDTEnable VOID EnterSIOconfig IOWriteByte (IoConfAddr,0x87); IOWriteByte (IoConfAddr,0x87); VOID ExitSIOconfig IOWriteByte (IoConfAddr,0xAA); VOID SetWDT IOWriteByte (IoConfAddr,0x2B); IOWriteByte(IoConfAddr+1, (IOReadByte(IoConfAddr+1)&0xFC)); // Procedure : AaeonWDTEnable AaeonWDTEnable () VOID WDTEnableDisable(1); // Procedure : AaeonWDTConfig AaeonWDTConfig (byte Counter, BOOLEAN Unit) VOID // Disable WDT counting WDTEnableDisable( // Clear Watchdog Timeout Status WDTClearTimeoutStatus();...
  • Page 92 WDTSetBit( TimerReg, UnitBit, Unit // WDT output mode set to pulse WDTSetBit( TimerReg, ModeBit, ModeVal // WDT output mode set to active low WDTSetBit( TimerReg, PolarityBit, PolarityVal // WDT output pulse width is 25ms WDTSetBit( TimerReg, PSWidthBit, PSWidthVal // Watchdog WDTRST# Enable WDTSetBit( DevReg, WDTRstBit, WDTRstVal WDTClearTimeoutStatus()

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