Mitsubishi Electric DD-5000 Service Manual page 47

Table 3-5-5 MD36710X (1/5)
Pin
Name
No.
Host Interface, CD-DSP interface, Sub ode interface (32 pins)
HD [15:12] When connecting HWID to V
become data lines 15:12 of 16 bit host
data bus. When connecting HWID to
GND, the lines become CD-DSP serial
input port pins defined as below.
3 CDERR (HD [15]) CD-DSP data error input
4 CDFRM (HD [14]) CD-DSP LR clock (frame) input
5 CDDAT (HD [13]) CD-DSP data input
6 CDDAT (HD [12]) CD-DSP bit clock input
HD [11:8] When connecting HWID to V
become data lines 11:8 of 16 bit host
data bus. When connecting HWID to
GND, the lines become sub code port
pins defined as below.
7 SCCLK (HD [11]) Sub code bit clock output
9 SCDAT (HD [10]) Sub code bit clock input
10 SCSYN (HD [9]) Sub code sync signal display input
11 SCFRM (HD [8]) Sub code frame sync input
12 HD [7:0] 8 I.s. host data bus. When connecting
14 HWID to GND, only the 8 I.s. signal is
| defined as a host data signal. When
16 connecting HWID to V
19 used for of 16 bit data bus.
|
21
22 HA [3:0] Host address input. Inputs address
24 signal that specifies physical address
25 inside MD36710X.
26
27 HWR# (HR/W#) Host protocol, type A
(HTYPE=GND): HR/W#. Decides
direction of host access.
Host protocol, type B (HTYPE=V
HWR#. Host writing input (active low).
29 H C S # Host chip select input. Active low.
30 HRD# (HDS#) Host protocol, type A (HTYPE=GND):
HDS#.
Data strobe input (active low).
Host protocol, type B (HTYPE=V
HRD#.
Host writing input (active low).
31 H R D Y Host ready output (active high). Use
this signal to transmit bit stream via
host bus. External pull-up resistor is
required.
Transmission of CodBurstLen byte
length is determined as 1 packet.
Check that the signal is active before
transmitting each packet. Possible to
write the bit stream serially up to
CodBurstLen byte to MD36710X.
32 HACK# Host acknowledge output (active low).
Protocol is type A, MD36710X asserts
this output and notify completion of
reading or writing cycle.
If this signal is not active, 3-state
condition occurs (External pull-up
resistor is required.).
If protocol is type B, the signal
functions as wait output signal. When
high speed host (microprocessor) is
used, this signal may not be used.
34 HIRQ# Interruption requirement (active low).
Deassert when host reads interruption
status resister of MD36710X. Also
deassert after host masks interruption in
the interrupt mask resister of
MD36710X or reseting.
If HIRQ# is not asserted, 3-state
condition occurs (External pull-up
resistor is required.)
Function
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3-27
Table 3-5-5 MD36710X (2/5)
Pin
Name
No.
35 HWID Determines data bus width of host
interface. It can be changed only
during reset. Host interface of
MD36710X is set to 8 bit width at low
level (GND) and set to 16 bit width at
high level (V
36 H O R D Determines byte order for data bus of
host interface in 16 bit width setting.
(HWID: V
It can be changed only during reset.
Set MD36710X to obtain I/O signals of
m.s. byte in HD [15:8] at low level
(GND) and those in HD [7:0] at high
level.
If HWID is GND level, connect to
GND.
37 H T Y P E Determines protocol of host bus. It
can be changed only during reset.
Sets MD36710X to type A at low level
and type B at High level.
130 STNDBY# Standby input (active low). All output
pins and bidirectional pins become
float state if asserting with RESET#
and MD36710X is cut electrically from
peripheral circuits. All internal
operation stop and power
consumption is confined to the
minimum.
Contents of SDRAM are not stored at
stanby.
141 R E S E T # Reset input (active low). Initializing
process of MD36710X starts at the
time deasserting is carried out from
assert state.
142 IDLE Idle, init or reset states display output
(active high).
GPI/O signal (4 pins)
2 G P S I General input controlled by DVP micro
code.
122 GPAI/O [1:0] General bidirectional pin controlled by
123 ADP micro code. After resetting, this
pin is defined as an input pin. ADP
command specifies the setting.
159 G P S O General output conrolled by DVP
micro code.
PLL signal (6 pins)
126 GCLK1 Master clock input for audio. Must
be connected to GCLK for usual
operation.
128 X O Output to the crystal connected to
GCLK. If the crystal is not used for
GCLK, XO is not connected.
129 G C L K Clock for main processor or crystal
input.
135 PLLCFG [1:0] PLL configuration input. It can be
137 changed only during reset. Both pins
must be connected to GND (digital)
for usual operation.
136 PLLCA Capacitor connection pin for PLL.
Connect the other terminal of the
capacitor to PLLGND.
Function
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DD
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