Decimal Point Counters Display Power Supply Timing Diagram IC Pinouts & Gate Construction Physical Layout and Connectors Sharp Compet 17 Calculator This schematic has been derived through reverse engineering. Section: Title and Contents This is not the manufacter’s schematic, nor Page: 1 Rendition: 2020 May 20 is it based on the manufacturer’s schematic.
S…, C… The state machine. Multiply or divide operation pending. ♦ This schematic includes the user memory which is not present in the Compet 17 model. Components marked with “§” Divide operation pending. are not present in the Compet 17.
(2nd operand, 48 bits) Decimal Point (PX) Ring Counter M Register (user memory, 48 bits) 12 Nixie Displays Display Latch 1-of-10 Decimal (4 bits) Decoder Point 000987654321. and Drivers Driver Sharp Compet 17 Calculator Section: Block Diagram Page: 3 Rendition: 2020 May 20...
(744 Hz) ØnD1 ØnD2 ØnD16 ØD1416 Øn(D16•B8•1) X and PXI with 000987654321. in the display. ØD n Digit being displayed (LSD) (MSD) One full number cycle in registers Sharp Compet 17 Calculator Section: Timing Diagram Page: 15 Rendition: 2020 May 20...
Controlling pin 6 allows it to function as a sample-and-hold latch, presumably relying on inter-electrode capacitance to hold the state between digit updates (see Display). Sharp Compet 17 Calculator Section: IC Pinouts and Gate Construction Page: 16 Rendition: 2020 May 20 1 ØnD3...