LG -D385 Service Manual page 208

<4-1-4-2_PMIC_PM8110_POWER>
NEED EXTERNAL OVP(28V)
Rev 0.4
C4158
VBUS_USB_IN
C4113 470n
+VPWR
C4114 C4115
1u 0.1u
+VPWR
2.2u C4120
C4121 C4122
22u 22u
2.2u C4123
2.2u C4124
2.2u C4125
+1V35_VSW_S3
+2V1_VSW_S4
+2V1_VSW_S4
+VPWR
+VPWR
BACKUP BATT
VCOIN
47uF
C4157
47u
LGE Internal Use Only
REV.0.5
117
VDRV_P
98 16V OVP
47p USB_IN_1
106
114
VCHG
USB_IN_2
107
83
GND_CHG_HP_1
VREG_IADC
116
GND_CHG_HP_2
111
49 TP4110
BATFET_CP_DRV
AVDD_BYP
99
113
VPRE_BYP VSW_CHG_1
115
VSW_CHG_2
103
VPH_PWR_1
104
VPH_PWR_2
112
VPH_PWR_3
80
VBAT_SNS
87
VBAT_1
95
VBAT_2
96
VBAT_3
38
VDD_S1 1.15V/2.5A/HF-SMPS
43
50
VREG_S1
GND_S1_1
37
51 VSW_S1_1
GND_S1_2
44
VSW_S1_2
65
VDD_S2 1.15V/3A/FT-SMPS
85
78
GND_S2_1 VREG_S2
86 72
VSW_S2_1
GND_S2_2
77
VSW_S2_2
94
VREF_NEG_S2
66
1.35V/1.5A/HF-SMPS
VDD_S3
74
79 VREG_S3
GND_S3
67
U4100
VSW_S3_1
73
VSW_S3_2
52
VDD_S4 PM8110 2.15V/1.5A/HF-SMPS
53
39 VREG_S4
GND_S4
45
VSW_S4
15
VDD_L1_2_3_4_5_1
31
22
1.225V/600mA/OFF VREG_L1
VDD_L1_2_3_4_5_2
36
1.2V/600mA/ON VREG_L2
6
1
1.15V/600mA/ON VREG_L3
VDD_L6_7_8_9_14_1
9 14
1.2V/300mA/OFF VREG_L4
VDD_L6_7_8_9_14_2
30
17
VDD_L6_7_8_9_14_3 1.3V/600mA/OFF VREG_L5
40
1.8V/300mA/ON VREG_L6
10
12
VDD_L10_11_13 2.05V/300mA/OFF VREG_L7
18
1.8V/50mA/ON VREG_L8
33
13 VREG_L9
VDD_L12_15_17_18_22 2.05V/600mA/OFF
4
1.8V/150mA/ON VREG_L10
8
VDD_L16_19_20_21_1 1.8V/5mA/OFF
35
24
1.8 or 2.85V/150mA/OFF VREG_L12
VDD_L16_19_20_21_2
1.8V or 2.95V/5mA/OFF
25
1.8V/300mA/OFF VREG_L14
27
1.8 or 2.85V/150mA/OFF VREG_L15
32
3.0V/600mA/OFF VREG_L16
29
2.95V/600mA/ON VREG_L17
5
1.8V or 2.95V/600mA/ON VREG_L18
16
2.85V/600mA/OFF VREG_L19
23
3.075V/50mA/ON VREG_L20
7
1.8V or 2.95V/150mA/ON VREG_L21
21
VREG_L22
1.8 or 2.85V/150mA/OFF
102
ATC_SINK
58
VIB_DRV_N PMIC_VIB_N
64
GND_DRV (Active Low)
59
C4143
VCOIN VCOIN
DNI
CCDS CARD Information
Release Date
2013. 08. 31
Based on Reference Schematic Rev.C
80-ND717-41 MSM8X10 + PM8110 REFERENCE SCHEMATIC
C4110 100n
L4110
+VPWR
1u
Note
Ensure that the BAT_SNS pin of the PMIC is connected
directly to the positive terminal of battery connector.
C4116
VBAT_SENSE
22u
Rev 0.4
C4117
VBAT
C4118 10u
4.7u
PSEUDO CAPLESS LDOs
L4,L6,L7,L10,L12,L14,L15,L20,L21 and L22
Note: If a decoupling capacitor of a pseudo capless LDO does not add up to 1uF
on the load side, install the capacitor close to the PMIC.
- 208 -
Rev 0.5
C4111 C4112
10u 120p
Note: Can be replaced with a single 10uF cap, 25V.
C4128
22u
NOTE
Connect GND of charger input capacitor, output capacitor, and GND_CHG_HP pins of PMIC together.
Connect the common point directly to the main GND using multiple vias.
Digital core, graphics, Apps DSP, USB core,
+1V15_VSW_S1
WLAN core, MSS, codec SDC
Rev 0.4
L4111
Note S1 is to be placed remotely near the MSM.
1u
+1V05_VSW_S2 Quad A7 processors
Rev 0.4
Rev 0.5
Note
L4112 470n
Please make sure the output capacitor of S2 is placed near the MSM,
and the positive (VREG_S2) and negative (VREF_NEG_S2) sense lines
are attached to the capacitor.
+1V35_VSW_S3
LDOs 1, 2, 3, 4, 5
L4113 2.2u
+2V1_VSW_S4
Codec analog; LDOs 6, 7, 8, 9, 10, XO, RFCLK, L14
L4114 2.2u
+1V225_VREG_L1 MSM analog 1, RF low-V
Pad1, LPDDR2, eMMC, MIPI_CS1
+1V2_VREG_L2
+1V15_VREG_L3 MSM memory & PLLs
Codec analog
+1V2_VREG_L4
+1V3_VREG_L5 WLAN ADC/DAC, RF low-V
Pad3, Pad7, WCN I/Os, LPDDR2, eMMC, Codec
+1V8_VREG_L6
+1V8_VREG_L7 Backup option
+1V8_VREG_L8 HK/XO ADC
+2V05_VREG_L9 RF high-V
+1V8_VREG_L10 MSM analog 2, PLLs, USB low-V; BB clock driver, RF I/Os, WCN XO
XO clock
+2V95_VREG_L12 UIM1, Pad5
RF clock drivers
+1V8_VREG_L14 MIPI I/Os, sensors, touchscreen, QFPROM programming
UIM2, Pad6
+2V95_VREG_L15
+3V3_VREG_L16 WCN PA, MIPI camera
eMMC
+2V95_VREG_L17
+2V95_VREG_L18 SD/eMMC
RF switches, GPS eLNA, MIPI_DSI1, cameras analog, sensors, touchscreen
+2V85_VREG_L19
+3V075_VREG_L20 USB high-V, microphone bias
+2V95_VREG_L21 Pad2 (SDC)
+2V85_VREG_L22 UIM3, Pad4
Rev 0.5
Copyright © 2014 LG Electronics. Inc. All right reserved.
6. CIRCUIT DIAGRAM
Only for training and service purposes