Memory Block; Security; Clock Distribution - Nokia NPM-6 Series Manual

CCS Technical Documentation

Memory Block

For the MCU the UPP includes 2 kbytes ROM, that is used mainly for boot code of MCU.
To speed up the MCU operation small 64 byte cache is also integrated as a part of the
MCU memory interface. For program memory 8Mbit (512 x 16bit) PDRAM is integrated.
RAM is mainly for MCU purposes but also DSP has also access to it if needed.
MCU code is stored into external flash memory. Size of the flash is 64Mbit (4096 x
16bit).

Security

The phone flash program and IMEI codes are software protected using an external secu-
rity device that is connected between the phone and a PC.

Clock distribution

32 kHz
UEM
Issue 1 01/03
Figure 12: Clock Distribution Diagram
VR3
VCTCXO
26MHz
32 kHz
SLEEPX
MCU
DSP
ãNokia Corporation.
System Module and User Interface
26 MHz
HELGA
26 MHz
UPP
SLICER
RFBUSCLK 13MHz
CBUSCLK 1MHz
DBUSCLK 13MHz
PLL
LCDCLK max. 6.5MHz
CTSI
SIMCLK max. 3.25MHz
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