Rf Interface Block; Combo Memory Module; Combo Memory Interface; Sram Memory Description - Nokia RH-27 Series Technical Documentation Manual

CCS Technical Documentation

RF Interface Block

The interface between the baseband and the RF module can be divided into two catego-
ries, the digital interface and the analog interface. The digital interface is between the
UPP and the RF chip. The serial digital interface is used to control the operation of the
different blocks in the RF chip. The analog interface is between the UEM and the RF. The
entire BB-RF interface is discussed in RF-BB Interface Specification RH-27.

Combo Memory Module

The RH-27 baseband memory module consists of a combo Flash/SRAM chip. It has
64Mbit burst-type flash memory and 4-Mbit of SRAM. In addition, the UPP has 8Mbit of
internal RAM. The UPP RAM is part of the UPP and is not covered here.

Combo Memory Interface

The memory interface consists of multiplexed address/data bus MEMADDA [23:0], the
MEMCONT[9:0] memory control bus, and GENIO[23] — which is used for memory control.
The purpose of the memory interface is to reduce the amount of interconnections by
multiplexing the address and data signals on the same bus. Because the required flash
address space is more than 16-bits, the MEMADDA[15:0] are multiplexed address/data
lines and MEMADDA[21:16] are only address lines, which in total allow for 4M addresses
(MEMADDA[21:0]). The multiplexed data/address lines require the memory to store the
address during the first cycle in the read/write access. Data access to the flash is per-
formed as a 16-bit access (MEMADDA[15:0]) in order to improve the data rate on the
bus. The memory interface supports asynchronous read, burst mode synchronous read,
and simultaneous read-while-write/erase — all controlled by the UPP.

SRAM Memory Description

The combo memory chip used in RH-27 has 4 Mbit of SRAM, 16-bits wide running at
1.8V. It uses a multiplexed address and data bus to minimize the pin count of the device.
Control signals are used to allow byte access to the device.

Flash Memory Description

The 64 Mbit density flash with 16-bit data access operates in both asynchronous random
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