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result of four most significant bits (7, 6, 5, 4)
7
7
6
6
5
5
4
4
result of inverting two most significant bits (7, 6)
7
6
5
4
replacement of bit (7) by external gate and
omission of bit (6)
7
6
5
4
fig. 4:
input sinusoidal signal
and individual binary gates
0
0.1
0.2
0.3
0
0.1
0.2
0.3
fig. 5:
input sawtooth signal
and individual binary gates
0
0.1
0.2
0.3
0
0.1
0.2
0.3
7
0.4
0.5
0.6
0.7
0.4
0.5
0.6
0.7
0.4
0.5
0.6
0.7
0.4
0.5
0.6
0.7
5
0
-5
0.8
0.9
1
7
6
5
4
3
2
1
0
0.8
0.9
1
5
0
-5
0.8
0.9
1
7
6
5
4
3
2
1
0
0.8
0.9
1
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