Main Block Diagram - Panasonic TH-50PV700AZ Service Manual

TH-50PV700AZ / TH-50PV700H / TH-50PV700M / TH-50PV700MR

15.2. Main Block Diagram

KEY SCAN G
AV4 IN
AV4 IN
KEY SW
S-VIDEO IN
VIDEO IN
L/R
AUDIO IN
HP_L/R
HEADPHONE
SU SCAN OUT
S.R
64
S.R
64
SC SCAN DRIVE
S.R
64
CONTROL
PULSE
S.R
64
SUSTAIN
PULSE
S.R
64
S.R
SCAN
64
PULSE
SD SCAN OUT
VOLTAGE
S.R
GENERATOR
64
SOS1
SOS2
S.R
64
S.R
64
S.R
64
AC CORD
S.R
64
S.R
64
S.R.
TH-50PV700AZ/H/M/MR
Main Block Diagram
K REMOTE/LED
POWER LED
K1
REMOTE RECEIVER
AI SENSOR
DG1
G51
H51
WOOFER
L L
SPEAKER
H11
R
AMP
SQ
L
WOOFER
L
R
SPEAKER
H12
R
AMP
SQ
R
TV-V
TUNER
SIF
MSP
L/R
MONITOR
OUT
TV_L/R
R,G,B
PC IN
AUDIO
INPUT
L/R
AUDIO
SELECT
IN
H6
DG6
L/R
AV1
V,Y,C
SUB
L/R
AV2
OUT
V,Y,PB,PR
MAIN
VIDEO
L/R
OUT
AV3
INPUT
V,Y,PB,PR
SELECT
H2 DG2
DC POWER H3
H AV TERMINAL,
AV SWITCH,MSP
DC POWER H4
+15V
SC20
P POWER SUPPLY
VSUS
SC2 P2
PROTECTION(SOS)
STANDBY STANDBY
RECTIFIER VOLTAGE VOLTAGE
CONTROL RECTIFIER
RUSH/MAIN_ON/OFF
RELAY,PFC
PROCESS
CONTROL
VOLTAGE
PFC_ON/OFF CONTROL
POWER
FACTOR
CORRECTOR
RELAY
SUSTAIN
LINE
P9 VOLTAGE
RECTIFIER
FILTER
CONTROL
C11
C1 DATA DRIVER(RIGHT)
VDA
C10 C20
S.R. S.R. S.R. S.R.
DG
DIGITAL SIGNAL PROCESSOR
DDR2x2
[27MHz]
VCXO X'tal
MAIN
MCU
D-LATCH
NOR
BOOT
MEM
FLASH
ROM
Peaks-Lite 2
D FORMAT CONVERTER,
PLASMA AI PROCESSOR
LVDS format
*CLK
*RGB:10bit(or8bit)
*VD,HD
DISPEN
GC3FS
DG5
D5
PROM
(4MByte)
DCLK
ASDIO
HDMI 1
DATA0
ADV/HDMI HDMI EQ
HDMI 2
DRVRST
OSD
DG11
MICOM
Discharge
Control(SC)
D20
P_ON/OFF
+5V
DC/DC CONVERTER
STBY5V_M P25 D25
+15V REG STB3.3V
PS_SOS RESET
RESET
+5Vc
POWER SOS
STB5V
PA3
VDA PA4
PROCESS
15Vc
P7
STB5V PA7
VOLTAGE
15Vd
RECTIFIER
+15V
P6 PA6 DC/DC
F_STB_14V F_STBY_15V
CONVERTER
15V
P12
Vda
PA
DC-DC CONVERTER
SUSTAIN
VSUS
VOLTAGE P11
RECTIFIER
GH HDMI3 IN
GH11
HDMI EQ
C21
C2 DATA DRIVER(CENTER)
VDA
C22 C32
S.R. S.R. S.R. S.R.
66
GS
SD CARD SLOT
DG52 GS52
DC/DC DC/DC DC/DC
3.3V 1.8V 1.2V
S POWER SW
STB_PS
S1
STB12V
16/32Mbit
RESET IC
Flash-ROM
FLASH CONTROL
SS34
128Mbit
DDR
CLOCK
GENERATOR
LATCH,SFVRST,SFRST
PD1-M plus
FCLK,FPDATA[1:0]
SS
*Sub Filed Processor
FPGA
*Plasma AI
*Discharge Control R[9:0]
G[9:0] SUSTAIN DRIVE
*H,V Snyc Control
B[9:0],HD,VD
*LVDS receiver
DCK
Discharge ADDRESS
Control(SS)
VOLTAGE
(VE)
Data Driver
Control
SUSTAIN
PULSE
XRST
ERASE
IIC2
PULSE
THERMAL SS_SOS8
WRITE PROTECT 32k
SENSOR
EEPROM
PCLK/NCLK
P3.3V
STB_PS/
P2.5V
STB12V
P1.2V
P5V
P5V
VDA
D32
D31
SS33 SS35 SS12
HDMI 3
VDA VDA
C3 DATA DRIVER(LEFT)
C35
SUSTAIN
CONTROL
C33
SS SOS
S.R. S.R. S.R.
TH-50PV700AZ/H/M/MR
Main Block Diagram
SD CARD SLOT
POWER
SWITCH
SS2
SS23
SS21
SS22
SS24
+15V
VSUS
SS3
SS11