HP 8340A Operating Manual page 173

Model 8340A
The leveling specifications apply to coupled operation, with no AM; in other words, ALC >
-10 dBm. Using decoupled mode or AM, the ALC level can be driven down to -20 dBm or
lower. At -20 dBm, the log amp slows down enough that high band accuracy is typically 1.5
dB at 150 nsec, 3.0 dB at 100 nsec. Decoupled mode can also be used to operate the ALC at
high levels and achieve better narrow pulse accuracy.
The above discussion applies to internal leveling only. Externally leveled pulse performance
will, of course, depend on the detector, but even with a perfect detector the external leveling
circuitry is not as fast. It typically will level pulses as narrow as 1 µ,sec, for detector outputs
above -40 dBV. An HP low barrier schottky detector driving 4 feet of 500 cable will realize
this performance, but a point contact type driving 4 feet of cable will slightly degrade
performance at 1 µ,sec.
Another type of leveling error arises from long pulse periods (low repetition rates), or more
precisely, long off times between pulses. The problem lies in the error detection and
modulator drive circuits shown in Figure 3-35. On the left is the comparison point, where
the ALC input is compared to the detector output. For this discussion assume the two
resistors are equal in value, so if the ALC and detector voltages are equal in magnitude but
opposite in polarity, the error signal will be zero. The error is fed to an integrator through
the integrate/hold switch. This switch is closed continuously during CW operation. Any
error signal causes the integrator output to change at a controlled rate (determined by
capacitor C), changing the RF output via the linear modulator. The integrator output
continues to change until its input is zero, which means the detector voltage is balancing the
ALC input voltage. The time required to cancel an error is about 70 µ,sec ( 4 µ,sec with AM on
or when sweeping fast, under which conditions a smaller value of C is switched into the
circuit).
DETECTOR OUTPUT
+1.0 v
ALC INPUT
-1.0 v
Consider now pulse operation with a period of 1 msec. The detector S/H measures a pulse
and holds its value until the next pulse. Assuming an error is present, the integrator
responds to that error, reaching the proper modulator drive in about 40 µ,sec. Since the
detector S/H is still holding the error from the last pulse, the integrator keeps changing until
the next pulse, overshooting its mark and causing instability. For this reason the integrate/
hold switch is only closed during a pulse. During the period between pulses, the switch is
opened, thus the integrator input is zero so the modulator drive doesn't change. This assures
that the amplitude at the beginning of the next pulse is the same as at the end of the
previous pulse. Corrections take place only during the pulses, until equilibrium is reached.
R
ERROR
VOLTAGE
0.0 v
R
Figure 3-35.
Error Detection and Modulator Drive
Scans by HB9HCA and HB9FSX
INTEGRATOR
INTEGRATE/HOLD
SWITCH
Operating Information
c
TO LINEAR
MODULATOR
3-109