Bit 7 A/D Done, Read Only; Figure 1-12. A/D Control Status Register - Brainboxes AD-1200 H User Manual

Reference
finished, its A/D Error and Clear Error bits are used to detect
and service A/D overrun or triggering mistakes. The DMA and
Interrupt enable bits are used to decide whether the A/D Done
bit causes a DMA read or system interrupt. Finally its Mode bits
determine whether single shot or continuous A/D conversions are
performed and what initiates the repetitive conversions and at
what rate they occur.

Figure 1-12. A/D Control Status Register.

___________________________________ _
ADCSR A/D Control Status Register.
BIT 7
0218 A/D
Hex DONE
Read

Bit 7 A/D Done, Read Only.

________________________
This bit is indicates that the A/D converter has a reading
ready.
Set By: The A/D converter when it has finished converting an
analogue input.
If Bit 3, DMA Enable, of the ADCSR is also set then
a DMA cycle will be generated when this bit is set by
the ADC.
If Bit 2, Interrupt Enable, of the ADCSR is also set,
but not Bit 3, then an interrupt will be generated when
this bit is set by the ADC.
Reset By:
Reading the ADC data high byte at Register 3.
This bit is automatically cleared at power up.
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BIT 6 BIT 5
A/D A/D
ERROR BUSY
Read Read
Analog Relay Mux Board
BIT 4 BIT 3
CLEAR DMA
ERROR ENABLE ENABLE BIT 1
Write R/W
BIT 2 BIT 1
INT MODE
R/W R/W
BIT 0
MODE
BIT 0
R/W