Signal Paths; Receiver Signal Paths - Nokia RH-37 Series Manual

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the RF ASIC (Helgo) except for the VCTCXO, VCO, and the loop filter.
The VCTCXO (Voltage Controlled Temperature Compensated Crystal Oscillator) generates
the clock frequency of 26 MHz. This frequency is buffered in the RF ASIC and fed to the
UPP. Additionally, it is used as the reference frequency for the RF PLL. The frequency of
the VCTCXO is locked into the frequency of the base station with the help of an AFC volt-
age which is generated in the UEM by an 11 bit D/A converter.
The PLL (phase locked loop) locks the VCO frequency into a stable frequency source,
given by the VCTCXO. The PLL is located in the RF ASIC and is controlled through the
RFBus.
The loop filter generates a DC control voltage for the VCO from the charge pump pulses
of the phase detector. The loop filter determines the step response of the PLL (settling
time) and contributes to the stability of the loop.

Signal paths

Receiver signal paths

HB BP
LC
LB LP
LC
ESD
FILTER
Antenna
Switch
1900 Tx 900 Tx
Module
LC LC
CTRL inputs
From the antenna-pad, the RF signal is fed directly to the antenna switch module.
Depending on the control signals VC1, VC2, VC3, the antenna port is connected to one of
the Rx ports RX1, RX2, RX3. From these ports the signal is passed on to the band filters:
• GSM 900: RX1‡GSM900 SAW filter
• GSM1800: RX2‡ GSM1800 SAW filter
• GSM1900: RX3‡ GSM1900 SAW filter
The antenna switch has the following typical insertion losses in the Rx mode from its
Issue 1 07/04
VLNA
1900 Rx
Balun
SAW
LNAB_P
LNA_P
1800 Rx
SAW
900 Rx
SAW
VBB
VR6
VLO
VR5
VPRE
VRF_RX
VR4
VF_RX
VPAB_VLNA
VDIG
VR3
VR2 VRF_TX
VBB
VCP
VR1
2.7V
10mA
GPIO
Rx part of RF ASIC
VRF_TX,VBB,VLO,VTX
Rx part of RF ASIC
©Nokia Corporation
VRF_RX
VF_RX
INTEGRATED
LOW-PASS FILTERS
AND AGC FUNCTION
BUILT-IN DC COMP.
VLO
Divide
by 2/4
RH-37
System Module
RXIP
RXQP
VBB
Bi-directional
RESET
Serial
SLE
SCLK
Interface
SDATA
VDIG
VR7
2 dB
Balun
Att
VCO Module
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