Sleep Mode - Nokia NPL-4 Series Manual

NPL-4/5/RM-104
System Module and User Interface
VR1A can be enabled or disabled. VR2 can be enabled or disabled and its output voltage
can be programmed to be 2.78V or 3.3V. VR4 -VR7 can be enabled, disabled, or forced
into low quiescent current mode. VR3 is always enabled in Active mode.
Regulator
VFLASH1
VAUX2
VAUX1
VAUX3
VANA
VIO
VCORE
VSIM
VR1A/VR1B
VR2
VR3
VR4
VR5
VR6
VR7
IPA1
IPA2
IPA3
VCAMDIG and
VANA_EXT

Sleep mode

Sleep mode is entered when both MCU and DSP are in stand–by mode. Both processors
control sleepmode.
Copyright © 2005 Nokia Corporation. All rights reserved.
Page 32
Table 17: Regulator Controls
NOTE
Enabled
Controlled by register writing
Default state is off.
Controlled by register writing.
Defaul start up setting 1.8V
Controlled by register writing.
Enabled
Disabled in sleep mode
Enabled
Enabled
Controlled by register writing.
Controlled by register writing
Disabled in sleep mode
Controlled by register writing
Disabled in sleep mode
Enabled
Disabled in sleep mode
Enabled
Disabled in sleep mode
Enabled
Disabled in sleep mode
Enabled
Disabled in sleep mode
Enabled
Disabled in sleep mode
Controlled by register writing.
Controlled by register writing.
Controlled by register writing
External regulators are controlled by
GenIO(01)
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Issue 2 05/05