Sharp CD-PC1881V Service Manual page 46

CD-PC1881V
IC2 VHiLC78631E-1: Servo/Signal Control (LC78631E) (1/2)
Pin
Terminal Name Input/Output
No.
1* VPDO Output
2 PD02 Output
3 PDO1 Output
4 AVSS —
5 FR —
6 AVDD —
7 ISET —
8 TAI Input
9 EFMO Output
10 VSS —
11 EFMI Input
12 TEST1 Input
13,14 CLV+, CLV- Output
15 V/P Output
16,17 TEST2, TEST3 Input
18* P4 Input/Output
19 HFL Input
20 TES Input
21* PCK Output
22* FSEQ Output
23 TOFF Output
24 TGL Output
25* THLD Output
26 TEST4 Input
27 VDD —
28,29 JP+, JP- Output
30*,31* SLD+, SLD- Output
32 EMPH_B Output
33* P5 Input/Output
34* LRCKO Output
35* DFLRO Output
36* DACKO Output
37* CONT1 Output
38 P0/DFCK Input/Output
39 P1/DFIN Input/Output
40 P2 Input/Output
41 P3/DFLR Input/Output
42 LRSY Output
43 CK2 Output
44 ROMXA Output
45 C2F Output
46 MUTEL Output
47 LVDD —
48 LCHP Output
49 LCHN Output
50 LVSS —
In this unit, the terminal with asterisk mark (*) is (open) terminal which is not connected to the outside.
Note: The same potential must be to the power terminals (VDD, VVDD, LVDD, RVDD, XVDD).
Unused input ports of general-purpose input/output ports (I/O) must be connected to 0V or set output port.
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Variable pitch PLL charge pump output.
Double-speed and mode playback PLL charge pump output.
Normal-speed mode playback PLL charge pump output.
Analog system ground. Normally 0V.
Built-in VCO frequency range setting resistor connection.
Analog system power supply.
PDO1 and PDO2 output current setting resistor connection.
Test input. A pull-down resistor is built in.
EFM signal output.
Digital system ground. Normally 0V.
EFM signal input.
Test input. A pull-down resistor is built in.
Spindle servo control output. CLV+ outputs a high level for acceleration, and CLV-outputs a high
level for deceleration.
Rough servo/phase control automatic switching monitor output. A high-level output indicates
rough servo, and a low-level output indicates phase control.
Test input. A pull-down resistor in built in.
I/O port.
Track detection signal input. This is a Schmitt input.
Tracking error signal input. This is a Schmitt input.
EFM data playback bit clock monitor. Outputs 4.3218 MHz when the phasw is locked.
Synchronization signal detection output. Output a high level when the synchronization signal
detected from EFM signal matches the internally generated synchronization signal.
Tracking off output.
Tracking gain switching output. Increase the gain when this pin outputs a low level.
Tracking hold output.
Test input. A pull-down resistor is built in.
Digital system power supply.
Track jump output. JP+ outputs a high level both for acceleration during outward direction jumps
and for deceleration during inward direction jumps. JP- outputs a high level both for acceleration
during inward direction jumps and for deceleration during outward direction jumps.
Slide output. This pin can be set to 1 of 4 levels by commands sent from the system control
microprocessor.
De-emphasis monitor. A high level indicates that disc requlring de-emphasis is being played.
I/O port.
LR clock output.
Digital filter outputs LR data output. The digital filters can be turned off with the DFOFF command.
Bit clock output.
Output port.
I/O port or digital filter bit clock input.
I/O port or digital filter data input.
I/O port. Used as the de-emphasis filter on/off switching pin in anti shock mode.
Port output or digital fllter LR clock input.
LR clock output.
Bit clock output. The polarity can be inverted with the CK2CON command.
ROMXA pins Interpolated data output. Data that has been interporated can be output by
issuing the ROMXA command.
C2 flag output.
Left channel mute output.
Left channel power supply.
One-bit D/A
Left channel P output.
converter pins
Left channel N output.
Left channel ground. Normally 0V.
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Function