Biostar M7TDB User Manual page 51

Chapter 2
Active to Precharge Delay
This item controls the number of DRAM clocks for active to precharge
delay.
The Choices: 6(default), 7, 5.
DRAM RAS# to CAS# Delay
This field lets you insert a timing delay between the CAS and RAS
strobe signals, used when DRAM is written to, read from, or refreshed.
Fast gives faster performance; and slow gives more stable performance.
This field applies only when synchronous DRAM is installed in the
system.
The Choices: 3(default), 2.
DRAM RAS# Precharge
If an insufficient number of cycle is allowed for RAS to accumulate its
charge before DRAM refresh, the refresh may be incomplete and the
DRAM may fail to retain data. Fast gives faster performance; and Slow
gives more stable performance. This field applies only when
synchronous DRAM is installed in the system.
The Choices: 3 (default),2.
DRAM Data Integrity Mode
This item select supported ECC or Non-ECC for DRAM.
The Choices: Non-ECC (default), ECC.
Memory Frequency For
The default is Auto.
Dram Read Thermal Mgmt
The Intel 845 Chipset MCH provides Memory Thermal Management
functionality to increase system reliability by decreasing thermal stress
on system memory and the Intel 845 Chipset MCH.
The Choices: Disabled (default), Enabled.
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at
F0000h~FFFFFh, resulting in better system performance. However, if
any program writes to this memory area, a system error may result.
The Choices: Disabled (default), Enabled.
2-14
BIOS Setup