Table of Contents
Advertisement
Section
IV
4-2
HIGH
, or "1"
•
+
2.4 V or greater
LOW. or
" O"
•
0 V
to
-+ 0.5
V
NANO
GATE
All
inputs must
be HIGH
to pro-
duce
a
LOW
output.
J
CLOCK
K
J-K
FLI P-FLOP
Q
When
Clock
input
goes
from
HI
GH
to LOW,
Q
outpu
t
assumes
level
of
J
input,
a
ou
tput
assumes
level
o
f
K input.
LOW
et
s
0 sets
Q
output
HIGH
.
LOW
at
R 0
se ts
Q
output
HIGH
.
FLIP-FLOP
A LOW at either
input
causes
the
co
rre sponding
output
to
be
HI
GH
.
Table
4·
2.
Logic
Symbols.
INVERTER
If input i
s HIGH,
output
is
LOW,
or
LOW input produces
HI
G
H
ou tput.
FLIP-FLOP
A
nega
tive-going
input
pulse
changes
the
state of
the flip-flop.
F
LI
P-FLOP
Model
3484A
A LOW
at eit
her
input
causes
the
co
rr
e~ponding
ou
tput
to
be
HI
GH.
.....
-
-.
-
Advertisement
Table of Contents
Troubleshooting
