Control Logic; Oscillator; Truth Table. Time/Div Setting Vs. Strobes For U637 And U638 - Tektronix 7B87 Instruction Manual

7 Output Clock Multiplexer. The Output Clock
MUltiplexer selects the output of the Internal Clock
Multiplexer, the Internal Clock divided by 1000, or the
signal from the EXT CLOCK IN connector to be the
"acquire clock" signal.
8. Intensify Circuit. The Intensify Circuit causes the
mainframe to intensify the display between sweep start
and the point selected by the ACQUIRE-STOP DELAY
control.
9. External Clock Buffer. The External Clock Buffer is a
high-impedance source follower which ensures that the
7B87 will not load the external signal source.
10. AQS CLOCKI AQR Switches. The AQS CLOCKI AQR
switches control the Output Clock Multiplexer and the
Intensify circuit.
CONTROL LOGIC
The Control Logic (CL) circuit produces a select input for
Output Multip!exer U660, and enable inputs for X1
multiplexer U638 and X10 multiplexer U637. The CL
circuit consists of U621A, U622A, B, C and D, and
U623B, C and D.
When section 18 or 35 of TIME/DIV switch S800 is
closed, U621A will be active and apply a high-logic level
to multiplexer U660's pin 15 input. One or both of
sections 18 and 35 is closed from 5s to 50 /ls/div, and
from 2 /lS to 50 /ls/div. Because of this, U621A applies a
high-logic level to U660's pin 15 input at all TIME/DIV
settings except 20, 10, and 5 /lS, and 20 and 10 ns.
Theory of
Operation~
7B87
Gates U622A, B, C and D and U623B, C and D are wired
so that they provide low-logic levels to the enable inputs
of: a) X1 multiplexer U638 from 5s to 10 /ls/div when
the MAG button is set to X1, and b) X10 multiplexer
U637 from 5s to 50 /ls/div when the MAG button is set
to X1 O. Table 3-1 is a truth table that gives details of this
operation.
When the TIME/DIV switch is set between 5 sand 10
/ls/Div, section 1 of S800 turns Q607 off. The high level
output of Q607 permits the Delay Time Comparator
(diagram 5) to operate. At settings between 5 /lS and 10
ns/Div, Q607 is turned on, producing a low output level
that disables the Delay Time Comparator.
OSCILLATOR
The Oscillator generates a 20.48-MHz signal that serves
as the reference for the clock-generating circuitry. Gates
U621 Band C and crystal Y626 form the Oscillator.
The Oscillator has two enable inputs, which are
connected to the TIME/DIV switch, via U622D, and to the
AQS CLOCKI AQR switch. Both enable inputs must be at
high-logic levels to allow oscillation.
When the TIME/DIV switch (S800) is set from 5 s to 10
/ls/Div, section 11 is closed. The ground from S800
section 11 causes U622D to assert a high-logic level to
U621 B's pin 5 input, which enables the oscillator.
When the AQS CLOCKI AQR control is set to INTERNAL
or INT .;- 1000, R646 applies a high-logic level to U621 C's
pin 10 input. When the AQS CLOCKI AQR control is set
TABLE 3-1
Truth Table. TIME/DIV Setting vs. Strobes for U637 and U638
Outputs
MAG U622C U622D U622B
5s to 50/ls
L L H H
- -
~-----
20
&
10/ls
L H
fl
H
- - - -
5/ls
L
H
2/ls to 50ns L L
-~---
---
20ns, 10ns
L H
---1---------
5s to 50/ls H L
20/ls, 10/ls
H H
5/ls
H H
2/ls to 50ns
H
L
20ns, 10 ns H H
'Operates from 55 to
10~s/div.
in X1 MAG.
20perates from 55 to
50~s/div.
in X10 MAG.
@
L H
L H
L H
H H
H L
L L
L H
L
L
Strobe for
U637
U622A U623C (U623D)
L
H
H
L
H
H
H L H
H L H
- -
H L H
L H
L2
H
L
H
H L H
H L H
H L H
Strobe for
U638
(U623B)
Ll
Ll
H
H
H
H
H
H
H
H
3-13