HP 3478A Technical Manual page 112

3478A 3478A
cuitry and Floating Common Logic Circuitry. cuitry and Floating Common Logic Circuitry.
Communications between the circuitry is done by the Communications between the circuitry is done by the
Isolation Logic. The circuitry Isolation Logic. The circuitry is described as
4-F-52. 2. Chass 4-F-5 Chassis Common Circu is Common Circuitry - paragra
55. 55.
a. a. Mai Main CPU (U n CPU (USO1 SO1) Cir
b. b. Con Contro trol ROM l ROM (U5 (U502)
c. c. Pow Power- er-On an On and Res d Reset Ci
59. 59.
d. d. CM CMOS R OS RAM - p AM - par arag
e. e. RAM RAM Add Addres ressin sing - p
f. f. Re Read adin ing th g the RA e RAM - p
g. g. Sen Sendin ding Dat g Data to th a to the RAM p
h. h. Key Keyboa board Op rd Opera eratio
i. i. Di Disp spla lay Op y Oper erat atio ion - pa
j. j. HP-IB Operation - paragraph 7-F-67. HP-IB Operation -
k. k. Rea Rear Pane r Panel Swit l Switch Cir
I. I. Voltm Vol tmete eter C r Comp omplet
m. m. Exter External T nal Tigger igger - par
7-F-53. 3. Isolat 7-F-5 Isolation Logic - parag ion Logic - paragraph 7-F
7-F-5 7-F-54. 4. Float Floating Common Logic Circui ing Common Logic Circuitry - paragraph
7-F-75. 7-F-75.
a. a. A/D A/D Contr Controller oller (U462 (U462) O
77. 77.
b. b. A/D C A/D Conv onvert erter Con er Contro
c. c. Inp Input H ut Hybr ybrid Co id Contr
d. d. Dig Digita ital to An l to Analo alog Con g Conver
paragraph 7-F-80. paragraph 7-F-80.
e. e. CPU R CPU Rese eset Ope t Operat
f. f. Front/ Fro nt/Rea Rear Swi r Switch tch Pos
7-F-55. 5. Chass 7-F-5 Chassis Commo is Common Circuit
7-F-56. The Chassis Com 7-F-56. The Chassis Common Circuitry
operation of the whole instrument, including front panel operation of the whole instrument, including front panel
and remote operat and remote operation. ion. The major circuitry The major circuitry is the Main
Controller Circuitry, consisting of a CPU (U501) and a Controller Circuitry, consisting of a CPU (U501) and a
Control ROM (U5 Control ROM (U502). 02). The operation The operation of the Chas
Common Circuitry is described in the following Common Circuitry is described in the following
paragraphs. Unless otherwise paragraphs. Unless otherwise specified, refer
Schematic 3 for the explanation. Schematic 3 for the explanation.
7-F-5 7-F-57. 7. Main CPU ( Main CPU (US01) Ci US01) Circuit
the CPU and associated circuitry is as follows: the CPU and associated circuitry is as follows:
a. a. The The CPU CPU has has an i an inte
memory and a cloc memory and a clock. k. The frequency and s The frequency and stability of the
clock is determined by 5.865 MHz crystal Y5O1. clock is determined by 5.865 MHz crystal Y5O1.
b. b. The D The Data ata Lin Lines ( es (DO to
used as both Data Lines and the lower 8 used as both Data Lines and the lower 8 bits of the
Address Lines (AO to Address Lines (AO to A7). A7). This is done by multiplex
is described as follows: follows:
itry - paragraph 7-F-
) Circui cuitry - pa try - parag ragrap raph 7-F h 7-F-57
02) - par - paragr agraph 7 aph 7-F- -F-58. 58.
et Circu rcuitr itry - par y - paragr agraph 7 aph 7-F-
agra raph 7 ph 7-F -F-6 -60. 0.
g - para aragra graph 7 ph 7-F- -F-61. 61.
M - par arag agra raph 7 ph 7-F -F-6 -62. 2.
e RAM para aragra graph - 7- ph - 7-F-6
tion - par n - paragr agraph 7 aph 7-F- -F-65. 65.
n - para ragr grap aph 7- h 7-F- F-66 66. .
paragraph 7-F-67.
ch Circui cuitry - pa try - parag ragrap raph 7-F h 7-F-68
lete - e - par paragr agraph aph 7-F 7-F-69 -69. .
- paragrap agraph 7- h 7-F-70. F-70.
raph 7-F-71. -71.
try - paragraph
) Operat peration-p ion-paragr aragraph
trol - para l - paragra graph 7- ph 7-F-7 F-78. 8.
ntrol - p ol - para aragra graph 7 ph 7-F- -F-79. 79.
verter ter Ope Operat ration - ion -
ration - ion - par paragr agraph 7 aph 7-F- -F-81. 81.
Positi ition - p on - para aragra graph 7- ph 7-F-8
n Circuitry ry
mon Circuitry controls the controls the
is the Main
of the Chassis
specified, refer to to
rcuitry ry. . The The operation operation of of
nterna rnal 12 l 128 by 8 bytes tes of R of RAM
tability of the
DO to D7) f D7) from rom the C the CPU ar PU are e
bits of the
This is done by multiplexing
the lines. The Address Lines are the lines.
Control ROM, CMOS RAM, and the HP-I Control ROM, CMOS
Data Lines send and receive data between the CPU and Data Lines send and receive data between the CPU and
the Control ROM, the Control ROM, CMOS RAM, and HP-I
ph 7-F- ALE (Address Latch Enable) line goes low to latch the ALE (Address Latch Enable) line goes low to latch the
lower 8 Address bits on US13. lower 8 Address bits
then sent to the Control ROM, CMOS ROM, and HP-IB then sent to the Control ROM, CMOS ROM, and HP-IB
-57. .
Chip. Chip.
c. c. Oth
-F-
Ports. The ports are used Ports.
and to send, and receive data between the Front Panel and to send, and receive data between the Front Panel
Pushbuttons and Isolation Logic. Pushbuttons and Is
data to the display (P20 to P23) are also used as data to the display (P20 to P23) are also used as the
upper Address bits (A8 to Al 1). upper Address bits (A8 to Al 1).
F-63. 3.
7-F-58. 7-F-58. Control ROM
addressed when its CE Line (Chip Enable at U502 pin addressed when its CE Line (Chip Enable at U502
20)is low. The low comes fr 20)is low.
-68. .
(Program Store Enable at USO1 pin 9). (Program Store
A7 comes from latch U513. A7 comes from
comes from Ports P20 to P23 (U501 pins 21 to 24). comes from Ports P20 to P23 (U501 pins 21 to 24).
Address bit A12 comes from Port P26 (U501 pin 37) of Address bit A12 comes from Port P26 (U501 pin 37) of
the CPU. the CPU. When the ROM is add
data from the ROM is transferred to the Data Lines. data from the ROM is transferred to the Data Lines.
7-F-59. Power-On and 7-F-59.
aph 7-F- 7-F-
and Reset Circuitry are used to reset the CPU after the and Reset Circuitry are used to reset the CPU after the
3478A is turned on, when the front panel TEST/RESET 3478A is turned on, when the front panel TEST/RESET
button is pressed, and if the CPU inadvertently goes to a button is pressed, and if the CPU inadvertently goes to a
non-operational state. . The circuitry oper non-operational state
a. a. Po
Schematic 3 and 4. The Power-On Circuitry Schematic 3 and 4.
CPU when the 3478A is turned on and when +SV power CPU when the 3478A is turned on and
F-82. 2.
supply is low. The step by step supply is low.
input of comparator USSOC goes high after the + SV input of comparator USSOC goes high after the + SV
power supply comes up. power supply comes up.
sis
AM
ing
7-F-17 7-F-17
The Address Lines are used to address t
RAM, and the HP-IB Chip.
CMOS RAM, and HP-IB Chip.
on US13. The Address bits ar
Other li er lines nes fro from th m the CPU e CPU are b
The ports are used to send data to to send data to the display
olation Logic. The ports used to
Control ROM (US102). (US102). The Contr
The low comes from the CPU's PSEN Line om the CPU's PSEN Line
Enable at USO1 pin 9). Address AO to
latch U513. Address bits A8 to Address bits A8 to All I
When the ROM is addressed and enabled,
Power-On and Reset Circuitr Reset Circuitry. y. The
The circuitry operates as follows:
Powe wer- r-On On Ci Circ rcui uitr try. y. Re Refe fer r t t o Figure 7-F-18
The Power-On Circuitry resets the
The step by step operation is as follows:
1. 1. Wh When t en the 3 he 347 478A i 8A is t
Figure Figure 7-F-18. 7-F-18. Power-On Power-On Circuitry
TM 11-6625-3071-14 TM 11-6625-3071-14
used to address the he
B Chip. The The
B Chip. The The
The Address bits are e
are bi-d i-dire irecti ctiona onal l
the display
The ports used to send send
the
The Control ROM ol ROM is is
pin
Address AO to
All I
ressed and enabled,
The Power-On Power-On
ates as follows:
o Figure 7-F-18, or , or
resets the
when +SV power
operation is as follows:
s tur urne ned on d on, t , the p he pos osit itiv ive e
Circuitry