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Transmeta Manuals
Computer Hardware
Crusoe TM5500
System design manual
Transmeta Crusoe TM5500 System Design Manual
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Contents
Table of Contents
Bookmarks
Table of Contents
Table of Contents
List of Tables
List of Figures
Chapter 1 Introduction and Naming Conventions
Overview
Naming Conventions
Power Management Mode Terms
Table 1: Supported ACPI Processor States
Table 2: Supported ACPI System States
Figure 1: Example Schematic Naming System
Power Network Names
Signal Names
Table 3: Power Net Naming Conventions
Table 4: Signal Naming Conventions
Reference Documents
Chapter 2 Example System Block Diagram and Schematics
System Block Diagram
Figure 2: Example System Block Diagram
Processor Schematics
Chapter 3 Processor Power Supplies and Power Management
Power Supplies
Core Power Supply Requirements
Table 5: Core Power Supply Requirements for TM5500/TM5800 Processors
Table 6: Default Power-On Start Voltage VRDA (VID) Output Codes
Table 7: VID/VRDA Values and Output Voltages for MAX1718 VRM
VRM Core Power Supply Example
Table 8: MAX1718 Core Power Supply Output Control Selector
Table 9: MAX1718 DSX Voltage Configuration
PLL Power Supply
Figure 3: PLL / Processor Core Voltage Tracking Requirement
I/O Power Supplies
Decoupling Capacitors
Power Supply Sequencing
Power Sequencing Requirements
Table 10: Power Supply Sequencing Timing Specifications
Figure 4: Power Supply Sequencing
Power Sequencing Circuit Examples
Power Supply Voltage Supervisor
POWERGOOD Block Diagram Example
State Transition Timing Requirements
Chapter 4 DDR Memory Design
DDR Memory Interface
Table 11: DDR SDRAM Memory Configurations
Clock Enable Isolation
Signal Termination
DDR Reference Voltage
DDR Reference Voltage Noise Filter Circuit
Figure 5: Recommended DDR Reference Voltage Circuit with Ferrite Bead Noise Filter
DDR Memory Interface Design Guidelines
PCB Placement and Routing Example
Figure 6: Recommended 4-Device DDR Memory Chip Placement
Figure 7: Recommended 4-Device DDR Memory Signal Routing - Top Layer
Figure 8: Recommended 4-Device DDR Memory Signal Routing - Internal Layer
Figure 9: Recommended 4-Device DDR Memory Signal Routing - Bottom Layer
DDR SDRAM Schematics
Chapter 5 SDR Memory Design
SDR Memory Interface
Table 12: SDR SDRAM Memory Configurations
SDR Memory Interface Design Guidelines
Bank Selection
Clock Enable Isolation During Power-Down States
Signal Termination
Miscellaneous Notes
SDR SDRAM Layout Notes
SDR SDRAM Memory Interface Timing
Example Design Strategy
Table 13: SDR SDRAM Interface Device Specifications
Figure 10: Physical SDRAM Configurations
Write Timing
Table 14: Write Timing Compensation
Read Timing
Figure 11: Read Timing Compensation
Uncertainty in the Feedback Calculation
Using Soldered-Down Memory
Figure 12: Adjustment of CLKIN Delay
Figure 13: Optimum Placement and Routing
Figure 14: Sub-Optimal Placement
Figure 15: Data Structure Diagram
Figure 16: Address Line Structure Diagram
Figure 17: Clock Line Structure Diagram
Figure 18: Data Mask Structure Diagram
Figure 19: Clock Enable Structure Diagram
Recommended Design Procedure
Design Example
SDR SDRAM Schematics
Chapter 6 System Design Considerations
Clocking
System Reset
Figure 20: System Reset Diagram
Signal Pull-Ups and Pull-Downs
Table 15: Signal Pull-Up/Pull-Down Requirements
Mode-Bit ROM
Code Morphing Software ROM
Serial Flash ROM Interface
Serial Flash ROM Write Protection Circuit
Table 16: PLD Pinout
Figure 21: Schematic Diagram of Serial Flash Write-Protection PLD in System
Combined BIOS/CMS Parallel ROM Interface
Southbridge
Qualified Southbridge Devices
Using CLKRUN
Southbridge Schematics
Figure 22: Recommended CLKRUN Circuit
Thermal Design
Thermal Diode and Thermal Sensor
Thermal Sensor Circuit
Thermal Sensor Issues
Thermal Sensor Layout
Thermal Sensor Example Schematic
TDM Debug Interface Connection
Figure 23: Transmeta Debug Connector (TDCA)
Chapter 7 PCB Layout Guidelines
PCB Design Layout
Example PCB Fabrication Notes
Board Design Guidelines
Printed Circuit Board Stackup
Allegro Standard Spacing Constraints
Table 17: Recommended Eight Layer PCB Stackup
Table 18: Standard Spacing/Line/Via Constraints
Allegro Extended Spacing Constraints
Allegro Extended Physical (Lines/Vias) Constraints
Allegro Extended Electrical (Lines/Vias) Constraints
Table 19: Extended Global Spacing/Line/Via Constraints
Table 20: Extended Physical Constraints
Table 21: Extended Electrical Constraints
Footprint and Pin Escape Diagram
Figure 24: Mechanical Footprint
Appendix A System Design Checklists
Appendix B Serial Write-Protection PLD Data
Figure 25: Write Protection TSSOP-24 JEDEC Fuse Map
Figure 26: Write Protection TSSOP-24 CUPL Source Code
Index
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TM5500/TM5800
System Design Guide
July 17, 2002
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