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Transmeta Crusoe TM5800 System Design Manual

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TM5500/TM5800
System Design Guide
July 17, 2002

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  • Page 1 TM5500/TM5800 System Design Guide July 17, 2002...
  • Page 2 Except as may be agreed in writing by Transmeta, all Transmeta products are provided “as is” and without a warranty of any kind, and Transmeta hereby disclaims all warranties, express or implied, relating to Transmeta’s products, including, but not limited to, the implied warranties of merchantability, fitness for a particular purpose and non-infringement of third party intellectual property.

  • Page 3: Table Of Contents

    July 17, 2002 Table of Contents List of Tables ............................5 List of Figures ............................7 Chapter 1 Introduction and Naming Conventions ....................9 Overview ............................. 9 Reference Documents ......................10 Naming Conventions ......................... 10 1.3.1 Power Management Mode Terms ................11 1.3.2 Power Network Names ....................
  • Page 4 Table of Contents July 17, 2002 SDR Memory Interface Design Guidelines................66 5.2.1 Bank Selection ......................66 5.2.2 Clock Enable Isolation During Power-down States .............67 5.2.3 Signal Termination ......................67 5.2.4 Miscellaneous Notes ....................67 SDR SDRAM Layout Notes.......................67 5.3.1 SDR SDRAM Memory Interface Timing ..............67 5.3.2 Example Design Strategy....................68 5.3.3...

  • Page 5: List Of Tables

    July 17, 2002 List of Tables Table 1: Supported ACPI Processor States ..............11 Table 2: Supported ACPI System States................11 Table 3: Power Net Naming Conventions................12 Table 4: Signal Naming Conventions ................12 Table 5: Core Power Supply Requirements for TM5500/TM5800 Processors ....22 Table 6: Default Power-on Start Voltage VRDA (VID) Output Codes........23 Table 7:...
  • Page 6 List of Tables July 17, 2002...

  • Page 7: List Of Figures

    Figure 21: Schematic Diagram of Serial Flash Write-protection PLD in System ....95 Figure 22: Recommended CLKRUN Circuit .................98 Figure 23: Transmeta Debug Connector (TDCA) ...............108 Figure 24: Mechanical Footprint ..................116 Figure 25: Write Protection TSSOP-24 JEDEC Fuse Map ..........124 Figure 26:...
  • Page 8 List of Figures July 17, 2002...

  • Page 9: Introduction And Naming Conventions

    • Chapter 2, Example System Block Diagram and Schematics presents the Crusoe TM5500/TM5800 processor in the context of a block diagram that shows necessary components and their connections. The reference schematic for the processor itself is also provided.

  • Page 10: Reference Documents

    1.2 Reference Documents The following documents are available from Transmeta for use in conjunction with this design guide. Some of these documents are extensively referenced in the design guide, and should be consulted as specified in the text.

  • Page 11: Power Management Mode Terms

    July 17, 2002 Introduction and Naming Conventions The following diagram shows how to locate the various schematic names: Figure 1: Example Schematic Naming System schematic name ball number pin name 1.3.1 Power Management Mode Terms The power management modes supported by TM5500/TM5800 processors are discussed in detail in Chapter 1, Functional Interface Description, in the Data Book.

  • Page 12: Power Network Names

    42. Power specifications for each of the supported power management modes are provided in Chapter 3, Electrical Specifications in the Data Book. 1.3.2 Power Network Names Transmeta’s reference schematics use a standard naming convention for power supply nets, provided in the table below. Table 3:...

  • Page 13: Chapter 2 Example System Block Diagram And Schematics

    The block diagram below shows major elements of a TM5500/TM5800 processor-based system design. Signals and bus interconnections are also shown. For detailed circuit design information, see the reference schematics throughout this document (also available in OrCAD format from your Transmeta representative). Figure 2:...
  • Page 14 • Transmeta Debug Module (TDM) Interface. This adds some low-level debug support to facilitate in- design bring-up, as well as connectivity to the Transmeta Virtual In-Circuit Emulator CE (TMVICE) for software development. See TDM Debug Interface Connection on page 107.

  • Page 15: Processor Schematics

    July 17, 2002 Example System Block Diagram and Schematics 2.2 Processor Schematics The following pages show TM5500/TM5800 processor reference schematics.
  • Page 16 DDR_DQM7_R DDR_DQM7 RN25C RN25D AB11 AC15 C_DQ63 C_DQMB7 Copyright (C) 1995-2001 Transmeta Project: TM5800 Design Guide Corporation. All rights reserved. This document contains confidential and Title: proprietary information of Transmeta TM5800 DDR Interface Corporation. It is not to be disclosed or used except in accordance with applicable agreements.
  • Page 17 SDR_DQ63_R SDR_DQM7_R RN49C RN49D SDR_DQ63 SDR_DQM7 S_DQ63 S_DQMB7 Copyright (C) 1995-2001 Transmeta Project: TM5800 Design Guide Corporation. All rights reserved. This document contains confidential and Title: proprietary information of Transmeta TM5800 SDR Interface Corporation. It is not to be disclosed or used except in accordance with applicable agreements.
  • Page 18 P_AD30 RSVD_G13 PCI_AD31 RSVD_E7_PD P_AD31 RSVD_E7 4.7K 4.7K Copyright (C) 1995-2001 Transmeta Project: TM5800 Design Guide Corporation. All rights reserved. This document contains confidential and Title: proprietary information of Transmeta TM5800 PCI Interface Corporation. It is not to be disclosed or used except in accordance with applicable agreements.
  • Page 19 TDM_SDA TDM_TRST# TDM_TDO TRST# TDM_TCK TDM_TMS TDM_TDI 4.7K Copyright (C) 1995-2001 Transmeta Project: TM5800 Design Guide Corporation. All rights reserved. This document contains confidential and Title: proprietary information of Transmeta TM5800 Sideband Corporation. It is not to be disclosed or used except in accordance with applicable agreements.
  • Page 20 POLY CVDD CVDD CVDD CVDD CVDD CVDD CVDD Copyright (C) 1995-2001 Transmeta Project: TM5800 Design Guide Corporation. All rights reserved. This document contains confidential and Title: proprietary information of Transmeta TM5800 PWR & GND Corporation. It is not to be disclosed or used except in accordance with applicable agreements.

  • Page 21: Chapter 3 Processor Power Supplies And Power Management

    July 17, 2002 Processor Power Supplies and Power Management C h a p t e r 3 Processor Power Supplies and Power Management This section provides design guidelines for TM5500/TM5800 processor power supplies, power sequencing, and power management circuits. This section also describes processor power supply requirements that must be implemented.

  • Page 22: Core Power Supply Requirements

    VRM vendors as indicated in this document. Note The only VRM qualified by Transmeta for TM5500/TM5800 processors is the Maxim MAX1718. Refer to the manufacturers VRM data sheet for detailed design information. Care must be taken to assure the core power supply voltage, V_CPU_CORE, supplied to TM5500/TM5800 processors does not exceed the absolute maximum limit of 1.5 V when evaluating TM5500/TM5800...

  • Page 23: Table 5: Core Power Supply Requirements For Tm5500/Tm5800 Processors

    July 17, 2002 Processor Power Supplies and Power Management Table 5: Core Power Supply Requirements for TM5500/TM5800 Processors (Continued) Specification Value Notes Source voltage 10.0 V minimum Required for this particular reference design to meet Combined ESR of bulk capacitors 5 mΩ...

  • Page 24: Table 7: Vid/Vrda Values And Output Voltages For Max1718 Vrm

    Processor Power Supplies and Power July 17, 2002 Management 3.1.1.2 VID/VRDA Code Table The VID/VRDA codes for the Maxim MAX1718 VRM are shown in the table below. Table 7: VID/VRDA Values and Output Voltages for MAX1718 VRM VID/VRDA Value VRDA [4] VRDA [3] VRDA [2] VRDA [1]...

  • Page 25: Vrm Core Power Supply Example

    3.1.2 VRM Core Power Supply Example The sections below provide an example core power supply design using the Maxim MAX1718 VRM. This reference design is recommended by Transmeta for TM5500/TM5800 processor-based system designs. Note Vendor part-specific information provided in this System Design Guide may be incorrect or out of date.

  • Page 26: Table 9: Max1718 Dsx Voltage Configuration

    Processor Power Supplies and Power July 17, 2002 Management Startup Mode Startup mode is selected when the ZMODE signal is high. In this mode the output voltage is determined by the internal impedance mode resister whose value is set on the rising edge of the ZMODE signal. The device looks at the impedance on the VID inputs.
  • Page 27 July 17, 2002 Processor Power Supplies and Power Management 3.1.2.3 Current Limit Adjustment (ILIM) Resistors in the example circuit are used to adjust the output current limit. The values are selected based on the maximum VRM current and the RDS of the lower switching FET being used.
  • Page 28 Processor Power Supplies and Power July 17, 2002 Management 3.1.2.8 VRM Shutdown Control (SKP/SDN#) When the SKP/SDN# input is low, the VRM is shut down. When this signal is pulled high to VCC, the VRM operates in skip mode. When this signal is left floating, the VRM operates in PWM mode. The reference design example operates in skip mode to take advantage of the high efficiency of skip mode at low currents.
  • Page 29 Setting shown is for VSNIFF_VCORE signal to reduce crosstalk noise. 0.900V Also R12 and R31 should be located as close the the VRM circuit as possible. Copyright (C) 1995-2000 Transmeta Project: TM5800 Design Guide Corporation. All rights reserved. This document contains confidential and...

  • Page 30: Pll Power Supply

    Processor Power Supplies and Power July 17, 2002 Management 3.1.3 PLL Power Supply Note See the Data Book for the voltage and current requirements for this and all power supplies. For all system designs, V_CPU_PLL for TM5500/TM5800 processors must track the core voltage from the maximum V_CPU_CORE value down to 1.0 V.
  • Page 31 2N2222A V_CPU_PLL LMV358 1N4148 30.1K 0.01uF 1000pF PLL_VDD, 1V Minimum Clamping Circuit Copyright (C) 1995-2001 Transmeta Project: TM5500/5800 System Design Guide Corporation. All rights reserved. This document contains confidential and Title: proprietary information of Transmeta PLL_VDD, 1V Min Clamp Circuit Corporation.
  • Page 32 Processor Power Supplies and Power July 17, 2002 Management Example PLL Power Supply Circuit Description R1/Q2 and R2 form a voltage divider to create a 1.0 V reference for the minimum V_CPU_PLL operating voltage. A high on START_SEQ (typically connected to the POWERGOOD output of the V_CPU_CORE regulator) turns on the PLL supply via FET Q2.

  • Page 33: I/O Power Supplies

    July 17, 2002 Processor Power Supplies and Power Management 3.1.4 I/O Power Supplies TM5500/TM5800 processors require a 3.3 V power supply (V3_3) and a 2.5 V power supply (V2_5) to power the I/O sections of the processor. If these supplies are derived from V3_3_STR and V2_5_STR, care must be taken to ensure the voltages are not glitched when these supplies are turned on.

  • Page 34: Decoupling Capacitors

    Processor Power Supplies and Power July 17, 2002 Management 3.1.5 Decoupling Capacitors V_CPU_CORE decoupling capacitors (8 x 0.1 µF X7R 0603) should be placed directly underneath the processor on the opposite PCB side (shown below). The V_CPU_CORE plane shown in the diagram below should extend significantly beyond the processor for connection to other peripheral decoupling capacitors.

  • Page 35: Power Supply Sequencing

    July 17, 2002 Processor Power Supplies and Power Management 3.2 Power Supply Sequencing Note See the Data Book for more information on power sequencing requirements for TM5500/TM5800 processors. 3.2.1 Power Sequencing Requirements In order to prevent a high startup current condition on the processor I/O power supplies, it is required that the processor core power supply (V_CPU_CORE) be turned on first and reach a level of V_CPU_CORE greater, prior to applying the processor 2.5 V and 3.3 V I/O voltages (V2_5 and V3_3, respectively).

  • Page 36: Power Sequencing Circuit Examples

    Processor Power Supplies and Power July 17, 2002 Management Under the above startup conditions the processor VDRA signals (that go to the VRM VID inputs) are not valid until the processor I/O voltages are present. Therefore, another method must be provided to supply valid VID signals to the VRM from the time the V_CPU_CORE core supply is enabled to the time the processor I/O voltages are within specifications.
  • Page 37 NOTE: Use either Voltage Sequence, Option 1 or Option 2, to generate the "FORCE_STARTUP_V" signal. Do not use both. Copyright (C) 1995-2001 Transmeta Project: TM5500/5800 System Design Guide Corporation. All rights reserved. This document contains confidential and Title: proprietary information of Transmeta Vcore Support Circuits Corporation.

  • Page 38: Power Supply Voltage Supervisor

    Processor Power Supplies and Power July 17, 2002 Management 3.3 Power Supply Voltage Supervisor The following page shows a power supply voltage supervisor reference design schematic.
  • Page 39 SOT23-6 VCC5 RST# PWRGOOD VCC3 VOL_SPR_2_5 RSTIN MANUAL_RST# Copyright (C) 1995-2001 Transmeta Project: TM5800 Design Guide Corporation. All rights reserved. This document contains confidential and Title: proprietary information of Transmeta Voltage Supervisor Corporation. It is not to be disclosed or used except in accordance with applicable agreements.

  • Page 40: Powergood Block Diagram Example

    Processor Power Supplies and Power July 17, 2002 Management 3.4 POWERGOOD Block Diagram Example The following page shows an example block diagram for possible system POWERGOOD circuits.
  • Page 41 Section 3.2 MANUAL_RST# THIS CIRCUIT ENSURES THAT THE CORE VOLTAGE IS AT LEVEL PRIOR TO ENABLING THE I/O VOLTAGES TO THE CPU Copyright (C) 1995-2001 Transmeta Project: TM5800 Design Guide Corporation. All rights reserved. This document contains confidential and Title:...

  • Page 42: State Transition Timing Requirements

    Processor Power Supplies and Power July 17, 2002 Management 3.5 State Transition Timing Requirements This section describes the state transition timing requirements for TM5500/TM5800 processors. Note that the various signal names used in this document are typically written from the perspective of the processor. For example, STPCLK# and SLEEP# refer to the processor input signals for Stop Clock and Sleep.
  • Page 43 July 17, 2002 Processor Power Supplies and Power Management Refer to the above table for a description of the notes in the diagrams below. Refer to Figure 4 and Table 10 for details on power supply sequencing timing. Power On (C0) PCI_RST# RESET# V_CPU_CORE,...
  • Page 44 Processor Power Supplies and Power July 17, 2002 Management ACPI Quick Start State (C2) The C0 to C2 transition is caused by the assertion of the STPCLK# signal. The processor issues a Stop Grant cycle in response to the STPCLK# assertion, then enters the C2 state. The C2 to C0 transition is caused by the deassertion of the STPCLK# signal.
  • Page 45 July 17, 2002 Processor Power Supplies and Power Management State Transition Timing Information/Requirements Diagram Note SLEEP# deassertion to STPCLK# 320 nS minimum recommended deassertion STPCLK# deassertion to C0 3 µS typical 5 µS maximum Refer to the above table for a description of the notes in the diagram below: Deep Sleep (C3) CPU_CLK STPCLK#...
  • Page 46 Processor Power Supplies and Power July 17, 2002 Management Refer to the above table for a description of the notes in the diagram below: System Sleep State (S1) CPU_CLK PCI_CLK STPCLK# Stop Grant SLEEP# execution ACPI Suspend-to-RAM State (S3) The C0 to S3 transition is typically caused by an I/O cycle to the power management controller. The I/O cycle that initiates the S3 sleep state is typically snooped by the processor.
  • Page 47 July 17, 2002 Processor Power Supplies and Power Management This type of system is expected to have a typical C2 entrance + exit latency of 8.5 µS, and a worst-case C2 entrance + exit latency of 15 µS. Example 2 (C3) A system designer may implement a system with the following C3 characteristics: •...
  • Page 48 Processor Power Supplies and Power July 17, 2002 Management LongRun Power Management LongRun power management is a power saving feature of TM5500/TM5800 processors that allows the processor to dynamically change its operating frequency and voltage in response to the instantaneous performance demands of running applications.
  • Page 49 July 17, 2002 Processor Power Supplies and Power Management LongRun Power Management Frequency Change ISR Executing* Force Grant* memory self-refresh* Core Clock Memory Clocks these traces do not represent hardware signals, but rather logical states. new clock multipliers/divisors written Voltage Change Mechanism The voltage change mechanism is extremely simple when compared to the frequency change mechanism.
  • Page 50 Processor Power Supplies and Power July 17, 2002 Management...

  • Page 51: Chapter 4 Ddr Memory Design

    July 17, 2002 C h a p t e r 4 DDR Memory Design This chapter provides guidelines for implementing DDR SDRAM memory interface designs for TM5500/TM5800 processors. Following the recommended DDR memory interface design rules and layout procedures will result in reliable system designs that maximize performance while minimizing power consumption.

  • Page 52: Clock Enable Isolation

    DDR Memory Design July 17, 2002 The frequency setting for the DDR SDRAM interface is initialized during the boot sequence from data stored in the configuration ROM. DDR interface frequency settings vary at each LongRun power management step. DDR interface timing specifications and operating frequencies at various LongRun power management steps are provided in the Data Book.

  • Page 53: Ddr Reference Voltage

    July 17, 2002 DDR Memory Design 4.4 DDR Reference Voltage The VDDIO25 power supply pins of the processor are connected to V2_5. The DDR interface has a DDR_VREF pin whose input should be derived from that power supply using a 1% resistor voltage divider. The specification for this input is described in the Data Book.

  • Page 54: Ddr Memory Interface Design Guidelines

    DDR Memory Design July 17, 2002 4.5 DDR Memory Interface Design Guidelines The DDR SDRAM interface operates at frequencies of 100-133 MHz. Use standard high-speed design, layout, and routing practices. Some specific guidelines in DDR memory layout are provided below. •...

  • Page 55: Pcb Placement And Routing Example

    July 17, 2002 DDR Memory Design 4.6 PCB Placement and Routing Example Device Placement The figure below shows the recommended TM5500/TM5800 processor and four DDR memory device placement using both sides of the PCB. Figure 6: Recommended 4-Device DDR Memory Chip Placement Bottom Bottom Place components one over...

  • Page 56: Figure 7: Recommended 4-Device Ddr Memory Signal Routing - Top Layer

    DDR Memory Design July 17, 2002 Primary Side (Top Layer) Signal Routing The figure below shows the connections from the TM5500/TM5800 processor to the DDR memory on the primary (top layer) side of the board. Figure 7: Recommended 4-Device DDR Memory Signal Routing - Top Layer...

  • Page 57: Figure 8: Recommended 4-Device Ddr Memory Signal Routing - Internal Layer

    July 17, 2002 DDR Memory Design Internal Layer Signal Routing The figure below shows the connections from the TM5500/TM5800 processor to the DDR memory on an internal layer of the board. Figure 8: Recommended 4-Device DDR Memory Signal Routing - Internal Layer...

  • Page 58: Figure 9: Recommended 4-Device Ddr Memory Signal Routing - Bottom Layer

    DDR Memory Design July 17, 2002 Secondary Side (Bottom Layer) Signal Routing The figure below shows connections from the TM5500/TM5800 processor to the DDR memory on the secondary (bottom layer) side of the board. Figure 9: Recommended 4-Device DDR Memory Signal Routing - Bottom Layer...

  • Page 59: Ddr Sdram Schematics

    July 17, 2002 DDR Memory Design 4.7 DDR SDRAM Schematics The following pages show DDR SDRAM reference schematics. • Single bank DDR soldered down (2 pages) • Single bank DDR SODIMM (2 pages) • DDR clock enable isolation circuit (1 page)
  • Page 60 DDR_CAS# DDR_MWE# DDR_BA0 DDR_BA1 DDRVREF DDRVREF 0.1uF 0.001uF Copyright (C) 1995-2001 Transmeta Project: TM5800 Design Guide Corporation. All rights reserved. This document contains confidential and Title: proprietary information of Transmeta Single Bank DDR Down (1/2) Corporation. It is not to be disclosed or used except in accordance with applicable agreements.
  • Page 61 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF Copyright (C) 1995-2001 Transmeta Project: TM5800 Design Guide Corporation. All rights reserved. This document contains confidential and Title: proprietary information of Transmeta Single Bank DDR Down (2/2) Corporation. It is not to be disclosed or used except in accordance with applicable agreements.
  • Page 62 DDR_SOD1_SA1 CBQ4 DDR_SOD1_SA0 CBQ5 CBQ6 CBQ7 CBQS CBDM Copyright (C) 1995-2001 Transmeta Project: TM5800 Design Guide Corporation. All rights reserved. This document contains confidential and Title: proprietary information of Transmeta Single DDR SODIMM (1/2) Corporation. It is not to be disclosed or used except in accordance with applicable agreements.
  • Page 63 VDD_33 GND_33 VREFA VREFB VDDSPD VDDID 0.1uF 0.001uF Copyright (C) 1995-2001 Transmeta Project: TM5800 Design Guide Corporation. All rights reserved. This document contains confidential and Title: proprietary information of Transmeta Single DDR SODIMM (2/2) Corporation. It is not to be disclosed or used except in accordance with applicable agreements.
  • Page 64 0.1uF QS3257 QUALITY SEMI SDR_CKE0 SDR_CKE_MUX0 SDR_CKE1 SDR_CKE_MUX1 A#/B Copyright (C) 1995-2001 Transmeta Project: TM5800 Design Guide Corporation. All rights reserved. This document contains confidential and Title: proprietary information of Transmeta CKE Quickswitch Corporation. It is not to be disclosed or used except in accordance with applicable agreements.

  • Page 65: Chapter 5 Sdr Memory Design

    July 17, 2002 C h a p t e r 5 SDR Memory Design This chapter provides guidelines for implementing SDR SDRAM memory interface designs for TM5500/TM5800 processors. Following the recommended SDR memory interface design guidelines and layout procedures will result in reliable system designs that maximize performance while minimizing power consumption.

  • Page 66: Sdr Memory Interface Design Guidelines

    SDR Memory Design July 17, 2002 The frequency setting for the SDR SDRAM interface is initialized during the boot sequence from data stored in the configuration ROM. SDR interface frequency settings vary at each LongRun power management step. SDR interface timing specifications and operating frequencies at various LongRun power management steps are provided in the Data Book .

  • Page 67: Clock Enable Isolation During Power-Down States

    July 17, 2002 SDR Memory Design 5.2.2 Clock Enable Isolation During Power-down States The processor SD_CKE[3:0] clock enable signals must be isolated from the SDR SDRAM. This is because power states exist where the processor is powered down and the SDR SDRAM remains powered (e.g. STR). The processor does not have a suspend power well, and like any CMOS circuit, the outputs are undefined for short periods of time during power transitions.

  • Page 68: Example Design Strategy

    SDR Memory Design July 17, 2002 The critical timing parameters of the processor memory controller and SDR SDRAM devices are shown in Table 13. The design rules described in this document satisfy these timings. Table 13: SDR SDRAM Interface Device Specifications Device Output Hold Time Input Setup Time...

  • Page 69: Write Timing

    It is important to note that this restriction is an original design limitation. The system may well be capable of successfully driving a longer line. However, Transmeta has not simulated this or designed for it, so violating this rule is done at the designer's risk.

  • Page 70: Read Timing

    SDR Memory Design July 17, 2002 5.3.4 Read Timing The processor memory controller has no information concerning the distance (and therefore delay) to and from the memory chips, but it must know when to expect valid data that is read from memory. The board designer must communicate this information by providing a carefully calibrated delay loop to resynchronize the data to the clock.

  • Page 71: Uncertainty In The Feedback Calculation

    July 17, 2002 SDR Memory Design 5.3.5 Uncertainty in the Feedback Calculation The JEDEC specification is very specific about the layout of the clock trace on the SODIMM, but only gives the total length of the other lines, including data. There will also be some variation of capacitive delays in boards due to geometry, number of vias, etc.

  • Page 72: Figure 13: Optimum Placement And Routing

    SDR Memory Design July 17, 2002 It is possible to place the SODIMM connector as in Figure 13 and avoid routing congestion. Placing the on- board memory on the far side of the SODIMM from the processor yields the optimum routing solution. Figure 13: Optimum Placement and Routing Crusoe CPU...

  • Page 73: Figure 15: Data Structure Diagram

    July 17, 2002 SDR Memory Design The JEDEC specification for SDRAM SODIMMs (JEDEC spec # JC42.5) is used to determine how to lay out the soldered-down memory traces to mimic the structure of an SODIMM. In the JEDEC specification the structure diagrams, with maximum and minimum lengths for each branch, are given for each trace.

  • Page 74: Figure 16: Address Line Structure Diagram

    SDR Memory Design July 17, 2002 The figures below show structure diagrams for each of the remaining SDRAM interface signals. Figure 16: Address Line Structure Diagram Address & Control - Dual SODIMM SODIMM Banks 2,3 SODIMM Banks 0,1 Address & Control - One SODIMM plus On-Board Memory JEDEC PC133 SODIMM LAYOUT 2nd Bank SEE: JC42.5...

  • Page 75: Figure 18: Data Mask Structure Diagram

    July 17, 2002 SDR Memory Design Figure 18: Data Mask Structure Diagram Data Mask (DQMB) - Dual SODIMM SODIMM Banks 2,3 SODIMM Banks 0,1 Data Mask (DQMB) - One SODIMM plus On-Board Memory JEDEC PC133 SODIMM LAYOUT SEE: JC42.5 TOTAL 0.00"...

  • Page 76: Recommended Design Procedure

    SDR Memory Design July 17, 2002 5.3.7 Recommended Design Procedure Determine the required memory configuration, soldered-down vs. SODIMM. Generate schematics. If soldered-down memory is used, the second resistor for termination of data lines must be added. If an advanced CAD package is used, apply delay rules to memory lines per Table 14. Also, add delay rules to match line lengths within signal groups.

  • Page 77: Design Example

    July 17, 2002 SDR Memory Design 5.3.8 Design Example The design example below assumes there is one bank of x8 memory soldered onto a 55 Ω board. The silicon is placed such that the Manhattan distance from most of the drivers is 4”. Follow the steps in the Recommended Design Procedure on page 76 to calculate length data to include in the feedback path (CLKIN).
  • Page 78 SDR_DQ62 SDR_DQ31 SDR_DQ63 DQ31 DQ63 SMBDATA SMBCLK DRAM / SDRAM Copyright (C) 1995-2001 Transmeta Project: TM5800 Design Guide Corporation. All rights reserved. This document contains confidential and Title: proprietary information of Transmeta Single SDR SODIMM Corporation. It is not to be disclosed or used except in accordance with applicable agreements.
  • Page 79 DQ62 SDR_DQ31 DQ31 DQ63 SDR_DQ63 SMBDATA_SDR0 SMBCLK_SDR0 DRAM / SDRAM Copyright (C) 1995-2001 Transmeta Project: TM5800 Design Guide Corporation. All rights reserved. This document contains confidential and Title: proprietary information of Transmeta Dual SDR SODIMM (1/2) Corporation. It is not to be disclosed or used except in accordance with applicable agreements.
  • Page 80 DQ62 SDR_DQ31 DQ31 DQ63 SDR_DQ63 SMBDATA_SDR1 SMBCLK_SDR1 DRAM / SDRAM Copyright (C) 1995-2001 Transmeta Project: TM5800 Design Guide Corporation. All rights reserved. This document contains confidential and Title: proprietary information of Transmeta Dual SDR SODIMM (2/2) Corporation. It is not to be disclosed or used except in accordance with applicable agreements.
  • Page 81 SMBCLK_SDR1 SMBCLK_SDR0 SMBDATA SMBDATA_SDR1 SMBDATA_SDR0 V3_3 7404 SPD_SELECT Copyright (C) 1995-2001 Transmeta Project: TM5800 Design Guide Corporation. All rights reserved. This document contains confidential and Title: proprietary information of Transmeta SMBus Isolation Corporation. It is not to be disclosed or used except in accordance with applicable agreements.
  • Page 82 0.1uF QS3257 QUALITY SEMI SDR_CKE0 SDR_CKE_MUX0 SDR_CKE1 SDR_CKE_MUX1 A#/B Copyright (C) 1995-2001 Transmeta Project: TM5800 Design Guide Corporation. All rights reserved. This document contains confidential and Title: proprietary information of Transmeta CKE Quickswitch Corporation. It is not to be disclosed or used except in accordance with applicable agreements.

  • Page 83: Chapter 6 System Design Considerations

    July 17, 2002 C h a p t e r 6 System Design Considerations 6.1 Clocking Note For detailed TM5500/TM5800 processor clock specifications see the Input Clocks section in the Data Book. The TM5500/TM5800 processor primary clock input (CLK_CPU0) requires a 60 or 66 MHz clock signal. This clock input is compatible with Pentium™...
  • Page 84 GND5 15pF 15pF PULL-DOWN SELECTS 2.5V SWING ON CPU CLOCK. PULL-DOWN SELECTS 24 MHZ ON UNUSED OUTPUT. Copyright (C) 1995-2001 Transmeta Project: TM5800 Design Guide Corporation. All rights reserved. This document contains confidential and Title: proprietary information of Transmeta ICS Clock Generator Corporation.
  • Page 85 INFORMATION REGARDING THE USE OF 4.7K THE FREE RUNNING PCI CLOCK FOR THE PROCESSOR AND SOUTHBRIDGE 15pF 15pF Copyright (C) 1995-2001 Transmeta Project: TM5800 Design Guide Corporation. All rights reserved. This document contains confidential and Title: proprietary information of Transmeta IMI Clock Generator Corporation.

  • Page 86: System Reset

    TM5500/TM5800 processors require the reset connections shown below for proper operation. This allows the Transmeta Debug Module (TDM) to assert JTAG reset and RESET# (needed for some debugging functions) without asserting PCI_RST#. A system-level PCI reset will also assert JTAG_TRST# and RESET#, which is needed for normal operation.

  • Page 87: Signal Pull-Ups And Pull-Downs

    July 17, 2002 System Design Considerations 6.3 Signal Pull-ups and Pull-downs The following signals should be pulled up to V2_5: IGNNE#, INTR, INIT#, NMI, FERR#, and SMI#. During the Deep Sleep power management state, the processor clock is stopped and most I/O pins are tri- stated (see the ACPI specification).
  • Page 88 System Design Considerations July 17, 2002 Table 15: Signal Pull-up/Pull-down Requirements (Continued) Processor Signal Pull-up / Pull-down Resistor Name Pin Number Type Value / Configuration 10 K Ω pull-down to ground Output CFG_SCLK DEBUG_INT Input DEBUG_NMI Input Input SROM_SIN Reserved and No Connection Signals 10 K Ω...

  • Page 89: Mode-Bit Rom

    Use of the external mode-bit ROM is required for guaranteed operation of all production parts. For more information, see the Development and Manufacturing Guide section Mode-Bit ROM Settings . Currently, the only Transmeta-approved configuration mode-bit ROMs are: • Microchip Semiconductor 93LC56B (128 x 16, 2 Kbit serial flash ROM).
  • Page 90 TDM_CFG_CS NC_U1_6 DO_U1 PCI_RST# CFG_CLK NC_U1_7 TDM_CFG_CLK 0.1uF Copyright (C) 1995-2001 Transmeta Project: TM5800 Design Guide Corporation. All rights reserved. This document contains confidential and Title: proprietary information of Transmeta Modebit ROM Corporation. It is not to be disclosed or used except in accordance with applicable agreements.

  • Page 91: Code Morphing Software Rom

    July 17, 2002 System Design Considerations 6.5 Code Morphing Software ROM TM5500/TM5800 processors use a combination of hardware and software to create an x86-compatible processor. A memory device of at least 1 MByte is required for storing Code Morphing software in compressed form prior to decompression and loading into RAM.
  • Page 92 TDM_SROM_CLK NC_22 NC_23 NC_24 NC_25 NC_26 NC_27 NC_28 Copyright (C) 1995-2001 Transmeta Project: TM5800 Design Guide Corporation. All rights reserved. This document contains confidential and Title: proprietary information of Transmeta CMS Serial Flash ROM Corporation. It is not to be disclosed or used except in accordance with applicable agreements.

  • Page 93: Serial Flash Rom Write Protection Circuit

    ROM to be inadvertently erased or modified in-system, which affects the Code Morphing software boot image stored in that ROM. Therefore, to ensure a high level of system security and integrity, Transmeta requires a special write protection circuit for the serial flash ROM. Systems using a parallel ROM to store the Code Morphing software boot image do not have this risk and do not require this write protection circuit.

  • Page 94: Table 16: Pld Pinout

    Voltage . The PLD must have 3.3 V outputs because the serial flash ROM is not 5 V-tolerant. • Power . Since the standard 22LV10 draws at least 70-90 mA from 3.3 V, Transmeta recommends a part with a power saving feature be used. Many vendors sell 22LV10 parts with power saving features.

  • Page 95: Figure 21: Schematic Diagram Of Serial Flash Write-Protection Pld In System

    July 17, 2002 System Design Considerations 6.5.2.4 Schematic The schematic below shows the serial flash ROM write-protection PLD circuit. Figure 21: Schematic Diagram of Serial Flash Write-protection PLD in System Notes: WP pull-up is in case GPIO powers up as an input If GPIO powers up low, tie 3.3V WPNEG high and change WP...

  • Page 96: Combined Bios/Cms Parallel Rom Interface

    These enhancements eliminate the need for this protection circuit. For debugging purposes, retain the serial flash connections to the Transmeta Debug Module (TDM) interface. The TDM has built-in serial flash and allows developers to boot from the TDM-based flash device.
  • Page 97 These signals act as bank selects to select either CMS sectors or BIOS. When CMS has decompressed and is ready to run x86 code, these signals select the highest bank (11) to allow access to the BIOS code. Copyright (C) 1995-2001 Transmeta Project: TM5800 Design Guide Corporation.

  • Page 98: Southbridge

    6.6 Southbridge 6.6.1 Qualified Southbridge Devices The Acer ALI M1535 southbridge has been fully qualified by Transmeta for use with TM5500/TM5800 processors, and is the recommended southbridge solution. Other PCI-interface southbridge devices can also be used with TM5500/TM5800 processors. Contact your Transmeta representative for qualification status of other southbridge devices.
  • Page 99 SIDEA2 SIDED12 SIDEIOR# SIDED13 SIDEIOW# SIDED14 SIDEDAK# SIDED15 Copyright (C) 1995-2001 Transmeta Project: TM5800 Design Guide Corporation. All rights reserved. NOTE: THIS SCHEMATIC IS FOR THE ALI 1535 SOUTHBRIDGE This document contains confidential and Title: proprietary information of Transmeta ALi 1535 Southbridge (1/4) ONLY.
  • Page 100 SA18 BIOSA18/GPO24/CLK_OFF# OSC32KI RTCAS OSC32KII RTCDS RTCRW CLK32KO Copyright (C) 1995-2001 Transmeta Project: TM5800 Design Guide Corporation. All rights reserved. NOTE: THIS SCHEMATIC IS FOR THE ALI 1535 SOUTHBRIDGE This document contains confidential and Title: proprietary information of Transmeta ALi 1535 Southbridge (2/4) ONLY.
  • Page 101 Keyboard & Mouse MSCLK/FPVEE MSDATA/IRQ12I IRRXH Infrared IRRX IRTX Copyright (C) 1995-2001 Transmeta Project: TM5800 Design Guide Corporation. All rights reserved. NOTE: THIS SCHEMATIC IS FOR THE ALI 1535 SOUTHBRIDGE This document contains confidential and Title: proprietary information of Transmeta ALi 1535 Southbridge (3/4) ONLY.
  • Page 102 GPIR#/GPO34 RUN_ENT1/GPIO1 GPOW/GPO35 RUN_ENT2/GPIO2 Miscellaneous RUN_ENT3/GPIO3 GPI25 Copyright (C) 1995-2001 Transmeta Project: TM5800 Design Guide Corporation. All rights reserved. NOTE: THIS SCHEMATIC IS FOR THE ALI 1535 SOUTHBRIDGE This document contains confidential and Title: ONLY. SEE THE VENDOR DOCUMENTATION FOR ALI 1535+ AND...

  • Page 103: Thermal Design

    0.13µ process technology used to manufacture TM5500/TM5800 processors. Transmeta strongly recommends die-referenced thermal solutions over PCB-referenced thermal solutions for new systems designed for TM5500/TM5800 processors. Die-referenced thermal solutions allow for possible improved packages with slightly different Z-axis dimensions in the future.

  • Page 104: Thermal Sensor Issues

    System Design Considerations July 17, 2002 6.8.2 Thermal Sensor Issues As mentioned, the thermal sensor chip generates a bias current for the diode. This current is on the order of 10-200 nA. This current is carried along the interconnect circuitry to the diode. On the way from the sensor to the diode (and back again) the current encounters two major sources of noise: •...

  • Page 105: Thermal Sensor Example Schematic

    July 17, 2002 System Design Considerations Do not allow other traces within 0.050” of the thermal pair. While electromagnetic fields may still be present, the gradient of those fields drops exponentially with distance. If the gradient is too large, the two traces are exposed to different field strengths, and the common-mode rejection of the sensor chip has no effect on this noise.
  • Page 106 NC_9 NC_13 NC_16 DIODE_ANODE ADD0 ADD1 2200pF DIODE_CATHODE Copyright (C) 1995-2001 Transmeta Project: TM5800 Design Guide Corporation. All rights reserved. This document contains confidential and Title: proprietary information of Transmeta Thermal Sensor Corporation. It is not to be disclosed or used except in accordance with applicable agreements.

  • Page 107: Tdm Debug Interface Connection

    ROM device to allow the TDM to override the active signal. The Transmeta Debug Module (TDM) communicates to the target through a high-density 30-pin flex cable known as TDCA. The TDCA is shown with connections to the core system. The TDM and the debug connection is used for flashing Code Morphing software ROM and the mode-bit ROM, connecting to the Transmeta ICE, and for other debugging purposes.

  • Page 108: Figure 23: Transmeta Debug Connector (Tdca)

    See the diagram below for the TDM interface pinout and signal descriptions. Figure 23: Transmeta Debug Connector (TDCA) Transmeta Debug Connector A The TDCA is a 30-pin, 0.5mm flex cable connector that has all vital signals needed to debug the Crusoe...
  • Page 109 TDM_TCK TDM_TMS TDM_TRST# TRST# SUSC# SUSC# SUSB# SUSB# Copyright (C) 1995-2001 Transmeta Project: TM5800 Design Guide Corporation. All rights reserved. This document contains confidential and Title: proprietary information of Transmeta TDM Connector Corporation. It is not to be disclosed or used except in accordance with applicable agreements.
  • Page 110 System Design Considerations July 17, 2002...

  • Page 111: Chapter 7 Pcb Layout Guidelines

    July 17, 2002 C h a p t e r 7 PCB Layout Guidelines Note The guidelines in this chapter must be followed for the design to meet specified TM5500/TM5800 processor operating frequencies. 7.1 PCB Design Layout • For thermal sensor/diode signal routing make sure to follow the guidelines in Thermal Diode and Thermal Sensor on page 103 .

  • Page 112: Example Pcb Fabrication Notes

    PCB Layout Guidelines July 17, 2002 • When transitioning signals between the return paths, insert a ground via next to the signal via, i.e. when transitioning from Signal 1 or Signal 2 to Signal 3, or when transitioning from Signal 3 or Signal 4 to Signal 1.

  • Page 113: Board Design Guidelines

    July 17, 2002 PCB Layout Guidelines 7.3 Board Design Guidelines The guidelines provided below were taken from TM5500/TM5800 processor-based reference designs using Allegro PCB layout tools. The dimensions are given in mils (1 mil = 1/1000 = 0.001 inch). 7.3.1 Printed Circuit Board Stackup Table 17: Recommended Eight Layer PCB Stackup Signal/Layer...

  • Page 114: Allegro Extended Spacing Constraints

    PCB Layout Guidelines July 17, 2002 7.3.3 Allegro Extended Spacing Constraints Table 19: Extended Global Spacing/Line/Via Constraints Constraint Name Default Constraint Value BGA Constraint Value Pin-to-pin 5 mils 5 mils Line-to-pin 5 mils 5 mils Line-to-line 5 mils 5 mils Via-to-pin Note Note...

  • Page 115: Allegro Extended Physical (Lines/Vias) Constraints

    July 17, 2002 PCB Layout Guidelines Table 19: Extended Global Spacing/Line/Via Constraints (Continued) Constraint Name Default Constraint Value BGA Constraint Value Test via-to-line 5 mils 5 mils Test via-to-shape 5 mils Note Buried blind via-to-buried blind via 10 mils 10 mils Buried blind via-to-line 5 mils 5 mils...

  • Page 116: Footprint And Pin Escape Diagram

    PCB Layout Guidelines July 17, 2002 7.4 Footprint and Pin Escape Diagram Figure 24: Mechanical Footprint SILKSCREEN OUTLINE PADSTACK SMT PAD = .030" DIA SOLDERMASK OPENING = .033" DIA PASTEMASK OPENING = .026" DIA...

  • Page 117: Appendix A System Design Checklists

    LongRun power management transitions. Designs that do glitch must include a low pass filter, isolated from down-stream logic, to remove the glitch from the regulator POWERGOOD output. Note that regulators qualified by Transmeta for TM5500/TM5800 processor have their POWERGOOD output blanked during transitions to alleviate this...
  • Page 118 100 mS negation of POWERGOOD that acts as a much better debounce filter than an external capacitor. The manual reset input of an independent monitor is an ideal place to connect the SYS-RST# pin of the Transmeta debug connector. ACPI System Power state support: •...
  • Page 119 July 17, 2002 System Design Checklists Power Supply Checklist Item Description Status If DDR memory is supported, the decoupling on 2.5 V STR at the DRAMs should be: • High frequency: approximately 3 low-ESL ceramic capacitors as close as possible to the power pins of each DRAM.
  • Page 120 The SMBus from the southbridge should not be connected to the Serial Debug Bus (i.e. pins SD_SCLK and SD_SDATA). The Serial Debug Bus must be connected to the Transmeta debug connector and be pulled up to V3_3 (IOVDD). If the Code Morphing software serial ROM is supported, the write protection PLD should be implemented.
  • Page 121 PCI clock, special routing considerations are necessary. See also Chapter 6, Using CLKRUN in the System Design Guide . The RESET# pin on the Transmeta debug connector must be connected to reset only the processor. The SYS_RST# pin on the Transmeta debug connector should be connected in such a manner as to reset the entire system when asserted.
  • Page 122 System Design Checklists July 17, 2002...

  • Page 123: Appendix B Serial Write-Protection Pld Data

    July 17, 2002 A p p e n d i x B Serial Write-protection PLD Data JEDEC Fuse Map and CUPL Source Code 24-Pin TSSOP The following text is the JEDEC file representing the fuse map for the write protection PLD. It was produced by the CUPL PLD design compiler for a 24-pin TSSOP package.

  • Page 124: Figure 25: Write Protection Tssop-24 Jedec Fuse Map

    Serial Write-protection PLD Data July 17, 2002 Figure 25: Write Protection TSSOP-24 JEDEC Fuse Map QP24* QF5892* L00000 11111111111111110111011111111111* L00032 11111111111111111111111111111111* L00064 11111111111111111111111111111111* L00096 11111111110110111111111111111111* L00128 11111111111111111111111110101111* L00160 11111111111111111111101111111111* L00192 11111011101111111111111111111111* L00224 01111111111111111011011111111111* L00256 11111111000000000000000000000000* L02144 00000000000011111111111111111111* L02176 11111111111111111111111111111111* L02208 11111111111011011111111111111111* L02240 11111111111101111111110111011111* L02272 11111111111111111111111101111111* L02304 11101110111111111111111111110000*...

  • Page 125: Figure 26: Write Protection Tssop-24 Cupl Source Code

    Serial Write-protection PLD Data Figure 26: Write Protection TSSOP-24 CUPL Source Code Name wrprotpd; PartNo Date 8/09/00; Revision 3; Designer Transmeta; Company Transmeta; Assembly 1; Location 1; Format /* Use JEDEC output format */ Device G22V10CP; /* This is the code for a 24-pin TSSOP package. */ /* The powerdown function on pin 4 is implied by */ /* this description.
  • Page 126 Serial Write-protection PLD Data July 17, 2002 Figure 26: Write Protection TSSOP-24 CUPL Source Code (Continued) Output pins PIN [18,19] = [Q0..1]; /* Flip-flops for the state machine */ PIN 17 = !CS0OUT; /* New serial flash */ PIN 23 = !CS1OUT;...
  • Page 127 July 17, 2002 Serial Write-protection PLD Data Figure 26: Write Protection TSSOP-24 CUPL Source Code (Continued) SEQUENCE [Q1..0] PRESENT BIT7 IF !DIN NEXT NO_PAT_MATCH; /* No write or erase opcode */ has bit 7=0 */ DIN & !SEL NEXT PAT_MATCH; /* For Atmel, bit 7=1 means a */ write or erase */ DIN &...
  • Page 128 Serial Write-protection PLD Data July 17, 2002...

  • Page 129: Index

    July 17, 2002 Index flash, serial (for Code Morphing software) write protection 93 Allegro spacing constraints 114 footprint 116 block diagram 13 interface, debugging 107 CD (DDR) port mechanical footprint 116 Clock Enable (CD_CKE) isolation 52 mode-bit ROM 89 power supply 53 signal termination 52 clocks 83 Code Morphing software serial flash 91...
  • Page 130 Index July 17, 2002...

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