Sign In
Upload
Manuals
Brands
Transmeta Manuals
Computer Hardware
Crusoe TM5500
Transmeta Crusoe TM5500 processor Manuals
Manuals and User Guides for Transmeta Crusoe TM5500 processor. We have
1
Transmeta Crusoe TM5500 processor manual available for free PDF download: System Design Manual
Transmeta Crusoe TM5500 System Design Manual (130 pages)
Brand:
Transmeta
| Category:
Computer Hardware
| Size: 1 MB
Table of Contents
Table of Contents
3
List of Tables
5
List of Figures
7
Chapter 1 Introduction and Naming Conventions
9
Overview
9
Naming Conventions
10
Power Management Mode Terms
11
Table 1: Supported ACPI Processor States
11
Table 2: Supported ACPI System States
11
Figure 1: Example Schematic Naming System
11
Power Network Names
12
Signal Names
12
Table 3: Power Net Naming Conventions
12
Table 4: Signal Naming Conventions
12
Reference Documents
10
Chapter 2 Example System Block Diagram and Schematics
13
System Block Diagram
13
Figure 2: Example System Block Diagram
13
Processor Schematics
15
Chapter 3 Processor Power Supplies and Power Management
21
Power Supplies
21
Core Power Supply Requirements
22
Table 5: Core Power Supply Requirements for TM5500/TM5800 Processors
23
Table 6: Default Power-On Start Voltage VRDA (VID) Output Codes
23
Table 7: VID/VRDA Values and Output Voltages for MAX1718 VRM
24
VRM Core Power Supply Example
25
Table 8: MAX1718 Core Power Supply Output Control Selector
25
Table 9: MAX1718 DSX Voltage Configuration
26
PLL Power Supply
30
Figure 3: PLL / Processor Core Voltage Tracking Requirement
30
I/O Power Supplies
33
Decoupling Capacitors
34
Power Supply Sequencing
35
Power Sequencing Requirements
35
Table 10: Power Supply Sequencing Timing Specifications
35
Figure 4: Power Supply Sequencing
35
Power Sequencing Circuit Examples
36
Power Supply Voltage Supervisor
38
POWERGOOD Block Diagram Example
40
State Transition Timing Requirements
42
Chapter 4 DDR Memory Design
51
DDR Memory Interface
51
Table 11: DDR SDRAM Memory Configurations
51
Clock Enable Isolation
52
Signal Termination
52
DDR Reference Voltage
53
DDR Reference Voltage Noise Filter Circuit
53
Figure 5: Recommended DDR Reference Voltage Circuit with Ferrite Bead Noise Filter
53
DDR Memory Interface Design Guidelines
54
PCB Placement and Routing Example
55
Figure 6: Recommended 4-Device DDR Memory Chip Placement
55
Figure 7: Recommended 4-Device DDR Memory Signal Routing - Top Layer
56
Figure 8: Recommended 4-Device DDR Memory Signal Routing - Internal Layer
57
Figure 9: Recommended 4-Device DDR Memory Signal Routing - Bottom Layer
58
DDR SDRAM Schematics
59
Chapter 5 SDR Memory Design
65
SDR Memory Interface
65
Table 12: SDR SDRAM Memory Configurations
65
SDR Memory Interface Design Guidelines
66
Bank Selection
66
Clock Enable Isolation During Power-Down States
67
Signal Termination
67
Miscellaneous Notes
67
SDR SDRAM Layout Notes
67
SDR SDRAM Memory Interface Timing
67
Example Design Strategy
68
Table 13: SDR SDRAM Interface Device Specifications
68
Figure 10: Physical SDRAM Configurations
68
Write Timing
69
Table 14: Write Timing Compensation
69
Read Timing
70
Figure 11: Read Timing Compensation
70
Uncertainty in the Feedback Calculation
71
Using Soldered-Down Memory
71
Figure 12: Adjustment of CLKIN Delay
71
Figure 13: Optimum Placement and Routing
72
Figure 14: Sub-Optimal Placement
72
Figure 15: Data Structure Diagram
73
Figure 16: Address Line Structure Diagram
74
Figure 17: Clock Line Structure Diagram
74
Figure 18: Data Mask Structure Diagram
75
Figure 19: Clock Enable Structure Diagram
75
Recommended Design Procedure
76
Design Example
77
SDR SDRAM Schematics
77
Chapter 6 System Design Considerations
83
Clocking
83
System Reset
86
Figure 20: System Reset Diagram
86
Signal Pull-Ups and Pull-Downs
87
Table 15: Signal Pull-Up/Pull-Down Requirements
87
Mode-Bit ROM
89
Code Morphing Software ROM
91
Serial Flash ROM Interface
91
Serial Flash ROM Write Protection Circuit
93
Table 16: PLD Pinout
94
Figure 21: Schematic Diagram of Serial Flash Write-Protection PLD in System
95
Combined BIOS/CMS Parallel ROM Interface
96
Southbridge
98
Qualified Southbridge Devices
98
Using CLKRUN
98
Southbridge Schematics
98
Figure 22: Recommended CLKRUN Circuit
98
Thermal Design
103
Thermal Diode and Thermal Sensor
103
Thermal Sensor Circuit
103
Thermal Sensor Issues
104
Thermal Sensor Layout
104
Thermal Sensor Example Schematic
105
TDM Debug Interface Connection
107
Figure 23: Transmeta Debug Connector (TDCA)
108
Chapter 7 PCB Layout Guidelines
111
PCB Design Layout
111
Example PCB Fabrication Notes
112
Board Design Guidelines
113
Printed Circuit Board Stackup
113
Allegro Standard Spacing Constraints
113
Table 17: Recommended Eight Layer PCB Stackup
113
Table 18: Standard Spacing/Line/Via Constraints
113
Allegro Extended Spacing Constraints
114
Allegro Extended Physical (Lines/Vias) Constraints
115
Allegro Extended Electrical (Lines/Vias) Constraints
115
Table 19: Extended Global Spacing/Line/Via Constraints
115
Table 20: Extended Physical Constraints
115
Table 21: Extended Electrical Constraints
115
Footprint and Pin Escape Diagram
116
Figure 24: Mechanical Footprint
116
Appendix A System Design Checklists
117
Appendix B Serial Write-Protection PLD Data
123
Figure 25: Write Protection TSSOP-24 JEDEC Fuse Map
124
Figure 26: Write Protection TSSOP-24 CUPL Source Code
125
Index
129
Advertisement
Advertisement
Related Products
Transmeta Crusoe TM5400
Transmeta Crusoe TM5600
Transmeta Crusoe TM5800
Transmeta Categories
Computer Hardware
More Transmeta Manuals
Login
Sign In
OR
Sign in with Facebook
Sign in with Google
Upload manual
Upload from disk
Upload from URL