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S-80735SN-DZ-T1 (SEIKO INSTR)+3.5 V
C-MOS VOLTAGE DETECTOR
—TOP VIEW—
NC
NC
2
1
OUT
5
4
V
DD
GND
3
1
2
3
OUT
V
GND
DD
V
DD
2
VOLTAGE
DETECT
1
OUT
3
GND
S-81250SGUP-DQD-T1 (SEIKO I&E)+5.0 V
THREE TERMINAL POSITIVE VOLTAGE REGULATOR
—TOP VIEW—
2
3
IN
OUT
GND
1
1
2
3
GND
IN
OUT
SA575DK-T (PHILIPS)
LOW VOLTAGE COMPANDOR
—TOP VIEW—
+V
1
1
V
20
IN
OP AMP
CC
+
NE575
_
_V
1
2
OP AMP
19
+V
2
IN
IN
+
_
V
1
3
18
_V
2
OUT
IN
RECTIFIER
3.9k
RECT.
1
4
17
V
2
IN
OUT
RECTIFIER
3.9k
C
1
5
16
RECT.
RECT
SUM
1
6
15
C
OUT
RECT
10k
SUM
AMP
_
COMP.
1
SUM
7
14
OUT
IN
+
SUM
AMP
10k
_
COMP.
V
8
13
REF
V
+
REF
10k
SUM NODE 2
GAIN CELL
1
9
12
IN
G
GAIN CELL
10k
GAIN CELL
10
GND
11
G
GAIN CELL
WRR-802A (U)
2
IN
2
2
2
IN
2
IN
TA31161FN(EL) (TOSHIBA)
IF DETECTOR
—TOP VIEW—
16
15
14
13
12
11
10
9
GND
V
2
CC
DETECTOR
RSSI
MIXER
IF AMP
LOCAL
OSC
GND
V
1
CC
1
2
3
4
5
6
7
8
OSC IN, OUT ;
: LOCAL OSC INPUT
BS
; BATTERY SAVE
MIXER OUT
; MIXER OUTPUT
DEC
; BIAS FOR IF INPUT
IF IN
; IF INPUT
RSSI
; RSSI OUTPUT
IF OUT1, 2
; IF LIMITTER OUTPUT
QUAD
; PHASE INPUT FOR FM DETECTOR
AF OUT
; DEMODULATION SIGNAL OUTPUT
MIX IN
; MIXER INPUT
TA8122AF (TSB)
TA8122AF(J.TP2)
CMOS SHIFT RESISTOR WITH LATCH
—TOP VIEW—
SIN
1
V
18
DD
OUT1
CK
2
17
OUT2
LATCH
3
16
OUT3
SOUT
4
15
EN
OUT4
5
14
RST
OUT5
6
13
OUT6
7
GND
12
OUT7
8
GND
11
OUT8
9
GND
10
OUT1
OUT2
17
16
5
EN
D
Q
D
Q
D
Q
C OB
C OB
C OB
R
R
R
3
LATCH
1
D
Q
D
Q
D
Q
D
SIN
C OB
C OB
C OB
C OB
R
R
R
R
2
CK
6
RST
SIN
: SERIAL DATA INPUT
CK
: SHIFT CLOCK INPUT
LATCH
: LATCH INPUT
SOUT
: SHIFT RESISTOR (FINAL STAGE)
OUTPUT
EN
: ENABLE INPUT
RST
: RESET INPUT
OUT1
OUT8
-
: SHIFT RESISTOR LATCH OUTPUT1-8
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
15
14
13
12
11
10
D
Q
D
Q
D
Q
D
Q
D
Q
C OB
C OB
C OB
C OB
C OB
R
R
R
R
R
Q
D
Q
D
Q
D
Q
D
Q
C OB
C OB
C OB
C OB
R
R
R
R
IC
4
SOUT
4-5
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