8.4
Diagram
10-4-9 TUNER
Block diagram
RF Input
Balun
Pinning information
B09, MxL661 (IC U104)
LNA
Synth
Calibration
Synth
2
I
C
CLK_OUT
VDD_3p3
1
LNA_INP
2
LNA_INN
3
VDD_1p8
4
5
AGC_2/GPO_3
6
AGC_1
Figure 8-6 Internal block diagram and pin configuration
IC Data Sheets
Channel
Filtering
RF
IF
Synth
Crystal
Reference
18
17
16
MxL661
15
14
13
back to
div.table
TPM15.5L LA
8.
Gain
Control
Voltage
Regulator
CLK_OUT
SDA
SCL
VDD_IO
GND_DIG
VDD_1p2
EN 35
IF1 Out
IF2 Out
AGC1
AGC2
19760_301.eps
2015-Aug-08