Spi Operation; Spi Data Transmission; Clock Polarity And Phase - IDTECH SecureHead User Manual

3. SPI OPERATION

This section describes the SPI (Serial Peripheral Interface), the SPI bus interface timing,
communication protocol, timeouts, and data output format.

3.1. SPI Data Transmission

A serial peripheral interface (SPI) is an interface that enables the serial exchange of data between two
devices, one called a master and the other called a slave. The host (master) generates the clock signal
(SPCK) to trigger data exchange on the SPI bus.
During each SPI clock cycle, the data is transmitted in both directions at the same time (full duplex
transmission)
- on the MOSI line, the master sends a bit and the slave reads it
- on the MISO line, the slave sends a bit and the master reads it
The SPI bus transmits data in an 8-bit data groups, sending data one bit at a time from MSB to LSB.
An example of bit transmission for byte A and byte B would be
A(bit 7) A(bit 6) ... A(bit 0) B(bit 7) B(bit 6) ... B(bit 0)

3.2. Clock Polarity and Phase

The clock polarity and phase can be configured with respect to the data. The serial clock input
frequency can go up to 400k bps.
When clock polarity =0 the base value of the clock is 0
1.2.
For clock phase=0, data are read on the clock's rising edge (low->high transition) and data
1 .2 .1 .
are changed on a falling edge (high->low transition).
For clock phase=1, data are read on the clock's falling edge and data are changed on a
1 .2 .2 .
rising edge.
When clock polarity=1 the base value of the clock is 1
1.3.
For clock phase=0, data are read on clock's falling edge and data are changed on a rising
1 .3 .1 .
edge.
For clock phase=1, data are read on clock's rising edge and data are changed on a falling
1 .3 .2 .
edge.
The signal is required to read card data from the device. See SPI clock phase and polarity property in
section 3 for commands to configure clock phase and polarity.The device defaults to clock phase = 0
and clock polarity = 0
The following picture shows an example of clock polarity=0 and clock phase=0. The data is read on
the rising edge of the clock and is changed on the falling edge. On MOSI line, the host sends out data
00000010, which is 02h.
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SecureHead SPI Interface with FPC User Manual
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