Table of Contents
Advertisement
Tabl
e
2-4
Connector
P4
PIA
Interface
Signals
.
PIN
SIGNAL
NUMBER
MNEMO
NI
CS
SIGNAL NAME AND DESCRIPTION
1
PBO-2
PERIPHERAL data line
(section
B.
bit
0,
PIA2)
- Negative True
Buffered
Output. This peripheral
data line
in the
B
section of
PIA2
(U30)
must be pro
-
grammed to
operate as an output. A
"1"
in
bit
0 of
the B data direction register causes
this line to function as
an output.
2
GND
GROUND -
Signal
return
line.
3
PBI-2
PERIPHERAL data line
(section
B,
bit
1,
PIA2)
-
Same as
PBO-2
on pin
1
except
bit 1
of
the B
data
direction
register
controls th is
line.
4
GND
GROUND -
Signal
return
line.
5
PB2-2
PERIPHERAL
data line (section
B,
bit
2, PIA2) - Same as
PBO-2
on
pin 1
except
bit
2 of
the B
data direction
register
controls this
line.
6
GND
GROUND -
Signal
return
line.
7
PB3-2
PER IPHERAL
data
line
(section
B,
bit3,
PIA2)
-
Same as
PBO-30n pin
1
except
bit
3 of
the B
data
di
rection
register
controls
this
line.
8
GND
GROU ND
- Signal
return line.
9
PB4-2
PERIPHERAL data line
(secti
on B,
bit
4,
PIA2) -
Negative
T
rue
Buffered
Input/
Output.
This peripheral data
line in
section
B
of
PIA2 (U21)
can
be
programmed to
operate either
as
an
input
line
(option) or as an output
line
(as
delivered
). A
"
0"
in bit 4 of
the B data
direction
register
causes
this line to
function
as an input and a
"1"
causes
this
line to function
as an output.
Through
the installation of
the
appropriate
device
and
jumper
connections on the
modu
le,
this line
is hardware
conf igured
to
function as an
input
or as an
ou tput
2-18
Advertisement
Table of Contents
