Pcie; Adcs - Digi ConnectCore 8X Hardware Design Manuallines And Checklist

Design checklist

PCIe

☑ Item Description
1. PCIe PICe interface is used in the Wireless variants of the SOM to connect the Wireless
interface MAC to the i.MX8X CPU. In non-wireless variants, this bus is available externally for
general purpose:
The remaining PCIe-related pads are unconnected in all variants: F4, F5, F6, F7, F8,
F9, G20, G21, G23, G24.
Leave this pins unconnected.
Decoupling capacitors in the transmission data lines must be set externally.

ADCs

☑ Item Description
1. Digi recommends you use VDD_ADC_1V8 as the CPU ADCs voltage reference, this
ADC_ means, connecting VDD_ADC_1V8 (pad AG24) to ADC_VREFH (pad J29).
VREFH
ConnectCore 8X Hardware Design Guidelines
Reference clock must be driven externally through the following pads:
n
G4: PCIE0_LGA_IN_REFCLK_P
l
G3: PCIE0_LGA_IN_REFCLK_N
l
Transmission data pair of the CPU (module output) is connected to the
n
following pads:
G10: PCIE0_LGA_OUT_TX0_P
l
G9: PCIE0_LGA_OUT_TX0_N
l
Receiver data pair of the CPU (module input) is connected to the following
n
pads:
G7: PCIE0_LGA_OUT_RX0_P
l
G6: PCIE0_LGA_OUT_RX0_N
l
PCIe
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