Table of Contents
Advertisement
Chapter 3
PXI Express Considerations
Notice that in a PXI chassis with more than eight slots, the PXI trigger lines may be divided into
multiple independent buses. Refer to the documentation for your chassis for details.
PXI_STAR Trigger
In a PXI Express system, the Star Trigger bus implements a dedicated trigger line between the
system timing slot and the other peripheral slots. The Star Trigger can be used to synchronize
multiple devices or to share a common trigger signal among devices.
A system timing controller can be installed in this system timing slot to provide trigger signals
to other peripheral modules. Systems that do not require this functionality can install any
standard peripheral module in this system timing slot.
An SC Express module receives the Star Trigger signal (PXI_STAR) from a system timing
controller. PXI_STAR can be used as an external source for many AI, AO, and counter signals.
An SC Express module is not a system timing controller. An SC Express module can be used in
the system timing slot of a PXI system, but the system will not be able to use the Star Trigger
feature.
PXIe_DSTAR<A..C>
PXI Express devices can provide high-quality and high-frequency point-to-point
connections between each slot and a system timing slot. These connections come in the
form of three low-voltage differential star triggers that create point-to-point, high-frequency
connections between a PXI Express system timing controller and a peripheral device. Using
multiple connections enable you to create more applications because of the increased routing
capabilities.
Table 3-1 describes the three differential star (DSTAR) lines and how they are used.
Trigger Line
PXIe_DSTARA
PXIe_DSTARB
PXIe_DSTARC
The DSTAR lines are only available for PXI Express devices when used with a PXI Express
system timing module. For more information, refer to the PXI Express Specification at
.
www.pxisa.org
3-2 | ni.com
Table 3-1. PXIe-DSTAR Line Descriptions
Distributes high-speed, high-quality clock signals from the system
timing slot to the peripherals (input).
Distributes high-speed, high-quality trigger signals from the system
timing slot to the peripherals (input).
Sends high-speed, high-quality trigger or clock signals from the
peripherals to the system timing slot (output).
Purpose
Advertisement
Table of Contents
