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Artesyn Embedded Technology MVME7100ET Programmer's Reference Manual

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MVME7100ET Single Board Computer
Programmer's Reference
P/N: 6806800K88B
June 2014

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Summary of Contents for Artesyn Embedded Technology MVME7100ET

  • Page 1 MVME7100ET Single Board Computer Programmer’s Reference P/N: 6806800K88B June 2014...
  • Page 2 © Copyright 2014 Artesyn Embedded Technologies, Inc. All rights reserved. Trademarks Artesyn Embedded Technologies, Artesyn and the Artesyn Embedded Technologies logo are trademarks and service marks of © Artesyn Embedded Technologies, Inc. 2014 Artesyn Embedded Technologies, Inc. All other product or service names are the property of their respective owners.

  • Page 3: Table Of Contents

    3.1.16 Watch Dog Timer Load Register ..........41 MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)
  • Page 4 4.13.3 Local Bus Controller Clock Divisor ..........68 MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)
  • Page 5 A.10 VPD Contents for MVME7100ET Boards ........
  • Page 6 Contents Contents Contents MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)
  • Page 7 MC864xD Interrupt Controller ........... 58 MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)
  • Page 8 Related Specifications ............94 MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)
  • Page 9 Boot Flash Bank ............32 MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)
  • Page 10 List of Figures MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)

  • Page 11: About This Manual

    This manual is divided into the following chapters and appendices: Chapter 1, Introduction, provides a brief product description and a block diagram showing the architecture of the MVME7100ET Single Board Computer. Chapter 2, Memory Maps, provides information on the memory maps of the board.
  • Page 12 Repeated item for example node 1, node 2, ..., node Omission of information from example/command that is not necessary at the time being Ranges, for example: 0..4 means one of the integers 0,1,2,3, and 4 (used in registers) MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)
  • Page 13 No danger encountered. Pay attention to important information Summary of Changes This is the first edition of this manual.. Part Number Publication Date Description 6806800K88A September 2010 First Release 6806800K88B June 2014 Re- branded to Artesyn template. MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)
  • Page 14 About this Manual About this Manual MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)

  • Page 15: Introduction

    Board Computer. Refer to the MC864xD Reference Manual listed in Related Documentation on page 91, for more details and programming information. At the time of publication of this manual, the MVME7100ET Single Board Computer is available in the configurations shown below. Table 1-1 Board Variants Marketing #...

  • Page 16: Features

    H/W switch or S/W bit write protection for entire logical bank NAND Flash Up to two devices available: 4 GB - 1 device  8 GB - 2 device  NVRAM One 512 KB MRAM extended temperature range Two 64 KB serial EEPROMs MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)
  • Page 17 VME64 Extensions (ANSI/VITA 1.1-1997) compliant (5 row backplane 160-pin VME connector) 2eSST (ANSI/VITA 1.5-2003) compliant Two five-row P1 and P2 backplane connectors One Tsi148 VMEbus controller Form Factor Standard 6U VME, one slot MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)
  • Page 18 User S/W controlled LED  Planar status indicators One standard 16-pin JTAG/COP header Boundary scan support Switches for VME geographical addressing in a three-row backplane Software Support VxWorks OS support Linux OS support MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)

  • Page 19: Block Diagram

    Introduction Block Diagram The following figure is a block diagram of the MVME7100ET architecture. Figure 1-1 Block Diagram MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)

  • Page 20: Functional Description

    I/O via the MVME7100ET transition module. The MVME7100ET provides front panel access to one serial port with a mini DB-9 connector and two 10/100/1000 Ethernet ports with two RJ-45 connectors. The front panel includes a fail indicator LED, user-defined indicator LED, and a reset/abort switch.

  • Page 21: Memory Maps

    Chapter 2 Memory Maps Overview The following sections describe the memory maps for the MVME7100ET. Refer to the MC864xD Reference Manual for additional details and/or programming information. 2.1.1 Default Processor Memory Map The following table describes a default memory map from the point of view of the processor after a processor reset.

  • Page 22: Pci Memory Map

    The following table is the suggested PCI memory map for each PCI bus. This table reflects the address map implemented by the board level firmware at release time. Table 2-3 PCI Memory Map PCI Address Start Size Definition Notes 0x00000000 top_dram - 1 dram_size System Memory (on-board DRAM) MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)

  • Page 23: Vme Memory Map

    PCI 1 I/O Space 1. CHRP-based addressing 2.1.4 VME Memory Map The MVME7100ET is fully capable of supporting both the PReP and the CHRP VME Memory Map examples with RAM size limited to 2 GB. MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)
  • Page 24 Memory Maps MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)

  • Page 25: Register Descriptions

    System resources including system control and status registers, external timers, and the QUART are mapped into a 16 MB address range accessible from the MVME7100ET local bus via the MC864xD LBC. The memory map is defined in the following table including the LBC bank chip select used to decode the register.
  • Page 26 COM 2 (QUART channel 1) F201 1FFF F201 2000 - COM 3 (QUART channel 2) F201 2FFF F201 3000 - COM 4 (QUART channel 3) F201 3FFF F201 4000 - COM 5 (QUART channel 4) F201 4FFF MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)
  • Page 27 External PLD Tick Timer 4 Counter Register F202 004C - Reserved F2FF FFFF F203 0000 NAND Chip 1 Data Register F203 0001 - Reserved F203 0FFF F203 1000 NAND Chip 2 Data Register F203 1001 - Reserved F203 FFFF MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)

  • Page 28: System Status Register

    2. 32-bit write only. 3. Byte read/write capable. 3.1.1 System Status Register The MVME7100ET has a System Status Register that is a read only register used to provide general board status information. Table 3-2 System Status Register System Status Register - 0xF200 0000...

  • Page 29: System Control Register

    A set condition indicates the switch is on. 3.1.2 System Control Register The MVME7100ET has a System Control Register that provides general board control bits. Table 3-3 System Control Register System Control Register - 0xF200 0001 Field...

  • Page 30: Status Indicator Register

    3.1.3 Status Indicator Register The MVME7100ET provides a Status Indicator Register that may be read by the system software to determine the state of the on-board status indicator LEDs or written to by system software to illuminate the corresponding on-board LEDs.

  • Page 31: Nor Flash Control/Status Register

    Reserved for future implementation 3.1.4 NOR Flash Control/Status Register The MVME7100ET Flash Control/Status Register provides software controlled bank write protect and map select functions as well as boot block select, bank write protect, and activity status for the NOR flash.
  • Page 32 Memory Map Select. When this bit is cleared, the flash memory map is controlled by the Flash Boot Block Select switch (see the MVME7100ET Installation and Use manual for switch settings). When the Map Select bit is set, boot block A is selected and...

  • Page 33: Interrupt Register 1

    Register Descriptions 3.1.5 Interrupt Register 1 The MVME7100ET provides an Interrupt Register that may be read by the system software to determine which of the Ethernet PHYs originated their combined (OR'd) interrupt. Table 3-6 Interrupt Register 1 Interrupt Register 1 - 0xF200 0004...

  • Page 34: Table 3-7 Interrupt Register 2

    RTC Mask. This bit is used to mask the RTC output. If this bit is cleared, the RTC output is enabled to generate an interrupt. If the bit is set, the RTC output is disabled from generating an interrupt. RSVD Reserved for future implementation. MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)

  • Page 35: Presence Detect Register

    Register Descriptions 3.1.7 Presence Detect Register The MVME7100ET provides a Presence Detect Register that may be read by the system software to determine the presence of optional devices. Table 3-8 Presence Detect Register Presence Detect Register - 0xF200 0006 Field...

  • Page 36: Nand Flash Chip 1 Control Register

    Register Descriptions 3.1.8 NAND Flash Chip 1 Control Register The MVME7100ET provides a Control Register for the NAND Flash device. Table 3-9 NAND Flash Chip 1 Control Register NAND Flash Chip 1 Control Register - 0xF200 0010 Field RSVD RSVD...

  • Page 37: Nand Flash Chip 1 Presence Register

    RSVD Reserved for future implementation. 3.1.10 NAND Flash Chip 1 Presence Register The MVME7100ET provides a Presence Register for the NAND Flash device. Table 3-11 NAND Flash Chip 1 Presence Register NAND Flash Chip 1 Presence Register - 0xF200 0014...

  • Page 38: Nand Flash Chip 1 Status Register

    Register Descriptions 3.1.11 NAND Flash Chip 1 Status Register The MVME7100ET provides a Status Register for the NAND Flash device. Table 3-12 NAND Flash Chip 1 Status Register NAND Flash Chip 1 Presence Register - 0xF200 00145 Field RSVD RSVD...

  • Page 39: Nand Flash Chip 2 Select Register

    RSVD Reserved for future implementation. 3.1.13 NAND Flash Chip 2 Select Register The MVME7100ET provides a Select Register for the NAND Flash device. Table 3-14 NAND Flash Chip 2 Select Register NAND Flash Chip 2 Select Register - 0xF200 0019...

  • Page 40: Nand Flash Chip 2 Presence Register

    Register Descriptions 3.1.14 NAND Flash Chip 2 Presence Register The MVME7100ET provides a Presence Register for the NAND Flash device. Table 3-15 NAND Flash Chip 2 Presence Register NAND Flash Chip 2 Presence Register - 0xF200 001C Field RSVD RSVD...

  • Page 41: Watch Dog Timer Load Register

    Ready/Busy 1. If cleared, Device 1 is busy. If set, device 1 is ready. RSVD Reserved for future implementation. 3.1.16 Watch Dog Timer Load Register The MVME7100ET provides a watch dog timer load register. Table 3-17 Watch dog timer Load Register Watch Dog Timer Control Register - 0xF200 0020 Field...

  • Page 42: Watch Dog Timer Resolution Register

    SYSRST System Reset. If cleared a board-level reset is generated when a time-out occurs. If set, a VMEbus SYSRST is generated when a time-out occurs. If MVME7100ET is SYSCON, then a local reset will also result in a VMEbus SYSRST.

  • Page 43: Watch Dog Timer Count Register

    32 s 64 s RSVD Reserved for future implementation. 3.1.19 Watch Dog Timer Count Register The MVME7100ET provides a watch dog timer count register. Table 3-20 Watch Dog Timer Resolution Register Watch Dog Timer Counter Register - 0xF200 0026 15:0 Field...

  • Page 44: Pld Revision Register

    Register Descriptions 3.1.20 PLD Revision Register The MVME7100ET provides a PLD revision register that can be read by the system software to determine the current revision of the timers/registers PLD. Table 3-21 PLD Revision Register PLD Revision Register - 0xF200 0030...

  • Page 45: Test Register 1

    Register Descriptions Version of the day 3.1.22 Test Register 1 The MVME7100ET provides a 32-bit general purpose read/write register which can be used by software for PLD test or general status bit storage. Table 3-23 Test Register 1 Test Register 1 - 0xF200 0038...

  • Page 46: External Timer Registers

    TEST1. 3.1.24 External Timer Registers The MVME7100ET provides a set of tick timer registers for access to the four external timers implemented in the timers/registers PLD. Note that these registers are 32-bit registers and are not byte writable.

  • Page 47: Control Registers

    ENINT Enable Interrupt. When the bit is set the interrupt is enabled. When the bit is cleared the interrupt is not enabled. CINT Clear Interrupt. INTS Interrupt Status. RSVD Reserved for future implementation. MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)

  • Page 48: Compare Register

    Tick Timer 1 Counter Register - 0xF202 0018 (32 bits) Tick Timer 2 Counter Register - 0xF202 0028 (32 bits) Tick Timer 3 Counter Register - 0xF202 0038 (32 bits) Tick Timer 4 Counter Register - 0xF202 0048 (32 bits) … MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)

  • Page 49: Geographical Address Register

    The VMEbus Status Register in the Tsi148 provides the VMEbus geographical address of the MVME7100ET. This register reflects the inverted states of the geographical address pins at the 5-row, 160-pin P1 connector. Applications not using the 5-row backplane can use the planar switch described in the MVME7100ET Installation and Use manual to assign a geographical address.
  • Page 50 Register Descriptions MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)

  • Page 51: Programming Details

     MC864xD Reset Configuration The MVME7100ET supports the power-on reset (POR) pin sampling method for processor reset configuration. The states of the various configuration pins on the processor are sampled when reset is deasserted to determine the desired operating modes. Combinations of pull-up and pull-down resistors are used to set the options.

  • Page 52: Table 4-1 Mc864Xd Por Configuration Settings

    0_10 LA[27] the 1.3GHz MPX Clock) processor 0_11 2.5:1 0_1000 for 1_00 1.067GHz processor 1_11 3.5:1 1_01 0_11 4.5:1 TSEC3_TXD[2] Resistor Core 1 Enable Core 1 disabled (no option Core 1 enabled disabled) MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)
  • Page 53 Local Bus GPCM - 16 1111 Local Bus GPCM -32 -bit TSEC1_TXD[0] Resistor 1 (no Alternate PCI-E 1 outbound ATMU option Boot Vector window 1 is enabled pulldown) Location Boot vector fetched from default boot ROM location MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)
  • Page 54 SerDes1: disabled SerDes2: x4 Serial RapidIO 1011 SerDes1: disabled SerDes2: x4 Serial RapidIO 1110 SerDes1: disabled SerDes2: x1/x2/x4/x8 PCIE 1111 SerDes1: x1/x2/x4/x8 PCI-E, 100 MHz ref clk SerDes2: x1/x2/x4/x8 MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B) PCI-E, 100 MHz ref clk...
  • Page 55 LGPL3, LGPL5 Testpoints Boot Normal I2C addressing Sequencer Extended I2C addressing Configuration Boot sequencer is disabled TSEC2_TXD[4] No Connects DDR SDRAM DDR1 Type TSEC2_TX_ER (default) DDR2 MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)
  • Page 56 No Connect Memory Debug information from Debug LBC is driven on the (processor Configuration D1_MSRCIDn and default) D1_MDVAL signals Debug information from DDR SDRAM controller is driven on the D1_MSRCID and D1_MDVAL signals MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)
  • Page 57 D1_MSRCID[1] No Connect DDR Debug DDR debug information Configuration is driven on the ECC pins (processor instead of the normal default) ECC I/O. DDR debug information is not driven on the ECC pins. MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)

  • Page 58: Mc864Xd Interrupt Controller

    Programming Details MC864xD Interrupt Controller The MVME7100ET uses the MC864xD integrated programmable interrupt controller (PIC) to manage locally generated interrupts. Currently defined external interrupting devices and interrupt assignments, along with corresponding edge/levels and polarities, are shown in the following table.

  • Page 59: Local Bus Controller Chip Select Assignments

    Not Used 1. Flash bank size determined by VPD flash packet. 2. Control/Status registers are byte read and write capable. 3. 32-bit timer registers are byte readable, but must be written as 32 bits. MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)

  • Page 60: I2C Device Addresses

    C controller is used by the system software to read the contents of the various I C devices located on the MVME7100ET. The following table contains the I devices used for the MVME7100ET and their assigned device addresses. Table 4-4 I2C Bus Device Addressing...

  • Page 61: User Configuration Eeprom

    Documentation, for additional details. VPD EEPROM The MVME7100ET board provides an 8 KB dual address serial EEPROM containing Vital Product Data (VPD) configuration information specific to the MVME7100ET. Typical information that may be present in the EEPROM may include: manufacturer, board revision, build version, date of assembly, memory present, options present, L2 cache information, and so on.

  • Page 62: Flash Memory

    BCM5482SH 4.10 Flash Memory The MVME7100ET is designed to provide 128 MB of soldered-on NOR flash memory. Two AMD +3.0 V devices are configured to operate in 16-bit mode to form a 32-bit flash bank. This flash bank is also the boot bank and is connected to LBC Chip Select 0 and 1. The NOR flash is accessed via the MC864xD local bus.

  • Page 63: Pci/Pci-X Configuration

    Device/Slot INT to MC864xD IRQ INTA# INTB# INTC# INTD# 0b0_0000 internal MC864xD (8641D) PCI1 0b0_0100 PMC1 INTA INTB INTC INTD Primary (PEX8114) IRQ1 IRQ2 IRQ3 IRQ0 0b0_0101 PMC1 INTB INTC INTD INTA Secondary IRQ2 IRQ3 IRQ0 IRQ1 MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)

  • Page 64: Pci Arbitration Assignments

    0x10B5 0x8112 PCI-E-to-PCI-X Bridge PEX8114 0x10B5 0x8114 VME Controller TSi148 0x10E3 0x0148 4.11.2 PCI Arbitration Assignments The integrated PCI/X arbiters internal to the PEX8112 and the PEX8114 provide PCI arbitration for the MVME7100ET. MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)

  • Page 65: Other Software Considerations

    Programming Details The arbitration assignments on the MVME7100ET are shown in the table below so that software may set arbiter priority assignments if necessary. Table 4-10 PCI Arbitration Assignments PCI Bus Arbitration Assignment PCI Master(s) PEX8114 REQ/GNT[0] PMC site 1 primary master...

  • Page 66: Clock Distribution

    PCI-E clock. Additional clocks required by individual devices are generated near the devices using individual oscillators. The following table lists the clocks required on the MVME7100ET along with their frequency and source. Table 4-12 Clock Assignments...

  • Page 67: System Clock

    The RTC clock input is driven by 1 MHz clock generated by the Control and Timers PLD. This provides a fixed clock reference for the MC864xD PIC timers, which software can use as a known timing reference. MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)

  • Page 68: Local Bus Controller Clock Divisor

    Programming Details 4.13.3 Local Bus Controller Clock Divisor The Local Bus Controller (LBC) clock output is connected to the PLD but is not used by the internal logic. MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)

  • Page 69: Programmable Configuration Data

    Overview This appendix provides data and specifications pertaining to programmable parts used on the MVME7100ET. The board is shipped after the programmable parts have been programmed through ATE or boundary scan according to the In-Circuit Test specifications. Table A-1 Programmable Devices...

  • Page 70: Vital Product Data (Vpd) Introduction

    Security information (VPD type, version and revision data, 32-bit CRC protection)  How to Read and Modify VPD Information vpdDisplay may be used to display VPD information. vpdEdit can be used to modify the VPD information. MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)

  • Page 71: What Happens If Vpd Information Is Corrupted

    The board may hang during startup (no-start condition).  The board may be very unstable if it reaches the prompt.  Device drivers, diagnostic tests, and firmware commands may hang or fail in unexpected  ways. MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)

  • Page 72: How To Fix Wrong Vpd Problems

    If you suspect that your board has problems, as a result of wrong VPD information, select SAFE mode by setting S1:1 ON and reboot the MVME7100ET. At this point, the firmware will ignore all EEPROM contents. Use the vpdEdit command to change the VPD to the correct parameters.
  • Page 73 (dataBitValue = 0; dataBitValue < 8; dataBitValue++) msbDataBitValue = (crcValue >> 31) & 1; crcValue <<= 1; if (msbDataBitValue ^ (dataByte & 1)) crcValue ^= 0x04c11db6; crcValue |= 1; dataByte >>= 1; crcValueFlipped = 0; MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)

  • Page 74: Serial Presence Detect Checksum Calculation

    The low order byte is the “Checksum”. Table A-3 Checksum Calculation Example SPD Byte Address Serial PD Convert to Decimal 00 (0x00) 0010 0100 > 01 (0x01) 1111 1110 > + 254 02 (0x02) 0000 0000 > MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)
  • Page 75 > > > 60 (0x3C) 0000 0000 > 61 (0x3D) 0000 0000 > 62 (0x3E) 0000 0000 > Decimal Total Divide by 256 Remainder Convert to binary 0010 0010 < 63(0x3F)(Checksum) 0010 0010 MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)

  • Page 76: Vpd Contents For Mvme7100Et Boards

    # of Bytes BINARY Board Type: Processor Board BINARY Architecture Revision BINARY Board Build Revision BINARY Revision Reason Flags BINARY Product Identifier Packet. Refer to Notes 1 and 2. BINARY # of bytes MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)
  • Page 77 Table A-4 Static VPD Contents (continued) Offset (HEX) Data (HEX) Field Type Description ASCII Product Identifier. Refer to Table A-5. BINARY Factory Assembly Number. Refer to Notes and 2. BINARY # of bytes MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)
  • Page 78 **Serial number to be filled in. Refer to Notes and 3. BINARY # of bytes ASCII Most significant serial number character Least significant serial number character BINARY External Processor Clock Frequency Packet BINARY # of bytes MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)
  • Page 79 Ethernet Controller 0 BINARY Ethernet MAC Address Packet BINARY # of bytes BINARY Six bytes containing the next Ethernet address. BINARY Ethernet Controller 1 BINARY Ethernet MAC Address Packet BINARY # of bytes MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)
  • Page 80 Ethernet MAC Address Packet BINARY # of bytes BINARY Six bytes containing the highest Ethernet address. BINARY Ethernet Controller 3 BINARY Processor Identifier Packet BINARY # of bytes ASCII Processor type Refer to Table A-5. MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)
  • Page 81 Flash bank number BINARY Flash access speed in nanoseconds: 0x6E = 110 ns BINARY Total bank size [(1<<n)*256K bytes]: 0x09 = 128 MB BINARY Bank 2 Flash Memory Configuration Packet BINARY # of bytes MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)
  • Page 82 3. This data is not static. Each board's Serial Number packet must be unique. The board's serial number is obtained from the onboard serial number label. MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)

  • Page 83: Table A-5 Variable Vpd Contents

    0x32 represents the assembly revision letter (A=41, B=42, and so on). Table A-5 Variable VPD Contents Offset (Hex) MVME7100ET-161 MVME7100ET-163 MVME7100ET-171 MVME7100ET-173 0106839D11* 0106839D12* 0106839D13* 0106839D14* Product Identifier (ASCII) Factory Assembly Number (ASCII) MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)
  • Page 84 Programmable Configuration Data Table A-5 Variable VPD Contents (continued) Offset (Hex) MVME7100ET-161 MVME7100ET-163 MVME7100ET-171 MVME7100ET-173 0106839D11* 0106839D12* 0106839D13* 0106839D14* Processor Type NAND Flash Size MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)

  • Page 85: Spd Contents For Mvme7100Et Boards

    Primary SDRAM Width: 0x08 = 8 bits 14 (0x0E) Error Checking SDRAM Width: 0x08 = 8 bits 15 (0x0F) Reserved 16 (0x10) SDRAM Device Attributes - Burst Lengths Supported: 0x0C = 4, and 8 burst lengths MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)
  • Page 86 Minimum RAS Pulse width (t RAS): 0x2D = 45ns. Refer to Note 3. 31 (0x1F) Module Bank Density: 0x01= 1GB 32 (0x20) Address and Command Setup Time Before Clock (t lS): 0x20 = 0.20ns. Refer to Note 3. MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)
  • Page 87 0x03 = Double refresh mode bit and High temperature self-refresh 50 (0x32) Not Used 51 (0x33) Not Used 52 (0x34) Not Used 53 (0x35) Not Used 54 (0x36) Not Used 55 (0x37) Not Used MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)
  • Page 88 68 (0x44) 69 (0x45) 70 (0x46) 71 (0x47) 72 (0x48) Module Manufacturing location. Refer to Note 5. 73 (0x49) Module Part Number. Refer to Note 5. 74 (0x4A) 75 (0x4B) 76 (0x4C) 77 (0x4D) MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)
  • Page 89 Module Manufacturing Date. Refer to Note 5. 94 (0x5E) 95 (0x5F) Module Serial Number. Refer to Note 5. 96 (0x60) 97 (0x61) 98 (0x62) 99 (0x63) Manufacturer's Specific Data. Refer to Note 5. 127 (0x7F) MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)
  • Page 90 1. This will typically be programmed as 128 bytes. 2. This will typically be programmed as 256 bytes. 3. From datasheet. 4. High order bit is self refresh “flag”. If set to “1”, the assembly supports self refresh. 5. Reserved. MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)

  • Page 91: Related Documentation

    4. In the Search text box, type the product name and click GO. Table B-1 Artesyn Embedded Technologies - Embedded Computing Publications Document Title Publication Number MVME7100ET Single Board Computer Installation and Use 6806800K87 MOTLoad Firmware Package User’s Manual 6806800C24 Manufacturers’...
  • Page 92 Revised Dec 2004 8-bit Universal Bus Transceiver and Two 1-bit Bus Transceivers with Split LVTTL Port, Feedback Path, and 3-state Outputs Exar ST16C554DIQ64 Version 4.0.1 Quad UART with 16-Byte FIFO's June 2006 Maxim Integrated Products MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)
  • Page 93 PLX Technology PEX 8112AA Version 1.2 ExpressLane PCI Express-to-PCI Bridge Data Book ExpressLane PEX 8114BC Version 3.0 PCI Express-to-PCI/PCI-X Bridge Data Book ExpressLane PEX 8525AA Version 0.95 5-Port/24-Lane Versatile PCI Express Switch Data Book MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)

  • Page 94: Related Specifications

    PCI-X Protocol Addendum to the PCI PCI-X PT 2.0a Local Bus Specification, Revision 2.0a July 22, 2003 Institute for Electrical and Electronics Engineers, Inc. Draft Standard for a Common P1386 - 2001 Mezzanine Card Family: CMC MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)
  • Page 95 Related Documentation Table B-3 Related Specifications (continued) Organization and Document Document Number Draft Standard Physical and P1386 - 2001 Environmental Layer for PCI Mezzanine Cards: PMC MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)
  • Page 96 Related Documentation MVME7100ET Single Board Computer Programmer’s Reference (6806800K88B)
  • Page 98 Artesyn Embedded Technologies, Artesyn and the Artesyn Embedded Technologies logo are trademarks and service marks of Artesyn Embedded Technologies, Inc. All other product or service names are the property of their respective owners. © 2014 Artesyn Embedded Technologies, Inc.

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