Sync Connector (Pin-Assignment, Hardware/Firmware); Pin Assignment Sync Connector, X51 (Cifx 80 90 104C); Items On Hardware; Items On Firmware - hilscher CIFX Series User Manual

Device Connections and Switches

9.11 SYNC Connector (Pin-Assignment, Hardware/Firmware)

9.11.1

Pin Assignment SYNC Connector, X51 (CIFX 80 90 104C)

9.11.2

Items on Hardware

Item Explanation
SYNC Signal 3.3 V (LVTTL), maximum load 6 mA
SYNC connector, X51 (for the PC cards cifX, as indicated under section Pin Assignment SYNC
Connector
Connector, X51 on page 164.)
Female connector, 3 pin, pitch spacing 1.25 mm (for example, the type Molex series 51021)
and female crimp contacts in design (e. g. type Molex series 50079/50058)
Max. Cable Recommendation: Max. 50 mm
Length
Note: Take EMC into consideration for the cable laying
9.11.3

Items on Firmware

Protocol
EtherCAT Slave
PROFINET IO
Device
sercos III Master
sercos III Slave
PC Cards cifX Compact PCI, Mini PCI, Mini PCIe, PCI-104 | Installation, Operation and Hardware Description
DOC120205UM53EN | Revision 53 | English | 2019-03 | Released | Public
Only for CIFX 80-RE, CIFX 90-RE\F, CIFX 90-RE\F\M12, CIFX 104C-RE,
CIFX 104C-RE-R, CIFX 104C-RE\F, CIFX 104C-RE\F\M12, CIFX 104C-
RE-R\F, CIFX 104C-RE-R\F\M12.
Pin Signal
1
GND
2
IO_SYNC0
3
IO_SYNC1
Table 123: Pin Assignment for SYNC Connector, X51
CIFX 90E-RE\F, CIFX 90E-RE\F\M12, CIFX 90E-RE\NHS\F, CIFX 90E-
RE\NHS\F\M12, CIFX 90E-RE\ET\F, CIFX 90E-RE\ET\F\M12, CIFX 90E-
RE\MR\F, CIFX 90E-RE\MR\F\M12 und CIFX 90E-RE\MR\ET\F, CIFX 90E-
RE\MR\ET\F\M12: The SYNC pins are on the Mini PCI Express bus (Pin
46, 44), refer to section Pin Assignment for Mini PCI Express Bus / SYNC
Connector (Bootstart), X1/X2, on page 168.
Table 124: SYNC Connector: SYNC Signal, Connector, Max. Cable Length
The loaded firmware determines if the signal is an input signal or output
signal. The following table shows the meaning of the SYNC signals for the
real-time Ethernet protocols currently offering SYNC signal support.
Signal IO_SYNC0
Input/Output
SYNC 0
Output
Bus cycle start (PROFINET IRT)
Output
External trigger to start bus cycle
Input
Rising edge
CON_CLK
Output
Table 125: Meaning of the SYNC Signals for each Protocol
Signal IO_SYNC1
Input/Output
SYNC 1
Output
-
-
DIV_CLK
Output
164/299
From
Remarks
Firmware
Version
- Configurable
3.4.x.x -
2.0.8.0 -
3.0.10.0 Configurable
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