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Seiko Epson S1C17153 Technical Manual

Cmos 16-bit single chip microcontroller
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CMOS 16-BiT SinGle ChiP MiCROCOnTROlleR
S1C17153
Technical Manual
Rev. 1.0

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Summary of Contents for Seiko Epson S1C17153

  • Page 1 CMOS 16-BiT SinGle ChiP MiCROCOnTROlleR S1C17153 Technical Manual Rev. 1.0...
  • Page 2 No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability...
  • Page 3 Tx : A socket for mounting Cx : Compiler package Sx : Middleware package Yx : Writer software Corresponding model number 17xxx: for S1C17xxx Tool classification C: microcomputer use Product classification S5U1: development tool for semiconductor products Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 4: Table Of Contents

    5.1.2 P0 Port Key-Entry Reset ...................5-1 5.1.3 Resetting by the Watchdog Timer ..............5-1 5.2 Initial Reset Sequence .....................5-2 5.3 Initial Settings After an Initial Reset ................5-2 6 interrupt Controller (iTC) .....................6-1 6.1 ITC Module Overview .......................6-1 Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)
  • Page 5 RTC Hour Counter Register (RTC_H) ..................8-9 9 i/O Ports (P) ........................9-1 9.1 P Module Overview ......................9-1 9.2 Input/Output Pin Function Selection (Port MUX) ..............9-2 9.3 Data Input/Output ......................9-2 9.4 Pull-up Control .........................9-3 9.5 Port Input Interrupt ......................9-3 Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)
  • Page 6 T16A Counter Ch.x Data Register (T16A_TCx) ..............11-14 T16A Comparator/Capture Ch.x Control Register (T16A_CCCTLx) ........11-14 T16A Comparator/Capture Ch.x A Data Register (T16A_CCAx) ..........11-16 T16A Comparator/Capture Ch.x B Data Register (T16A_CCBx) ..........11-16 Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)
  • Page 7 15 SPi ..........................15-1 15.1 SPI Module Overview ....................15-1 15.2 SPI Input/Output Pins ....................15-1 15.3 SPI Clock ........................15-2 15.4 Data Transfer Condition Settings ...................15-2 15.5 Data Transfer Control ....................15-3 15.6 SPI Interrupts ........................15-5 Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)
  • Page 8 18.2 Comparison Voltage Setting ..................18-1 18.3 SVD Control ........................18-2 18.4 Control Register Details ....................18-2 SVD Enable Register (SVD_EN) ....................18-2 SVD Comparison Voltage Register (SVD_CMP) ..............18-3 SVD Detection Result Register (SVD_RSLT) ................18-4 Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)
  • Page 9 B.2 Reducing Power Consumption via Power Supply Control ........... AP-B-3 appendix C Mounting Precautions ................aP-C-1 appendix D Measures against noise ................ aP-D-1 appendix e initialization Routine ................aP-e-1 appendix F Mask ROM Code Development .............. aP-F-1 Revision history Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 10: Overview

    1 OVeRVieW Overview The S1C17153 is a 16-bit MCU featuring ultra-low-power operations and compact dimensions in die form. The S1C17153 is ideal for battery-driven electronic equipment, such as OTP cards, eTokens, and remote control units with a simple display. Features The main features of the S1C17153 are listed below.

  • Page 11: Block Diagram

    (1 ch.) CAPB0/TOUTB0 SIN0, SOUT0, UART (1 ch.) Sound generator BZ, #BZ SCLK0 SDI0, SDO0, I/O port/ SPI (1 ch.) SPICLK0, P00–07, P10–13 port MUX #SPISS0 Figure 1. 2.1 S1C17153 Block Diagram Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 12: Pads

    SEG24 SEG25 SEG26 SEG27 1.781 mm Figure 1. 3.1.1 S1C17153 Pad Configuration Diagram Chip size X = 1.781 mm, Y = 1.952 mm Pad opening X = 68 µm, Y = 68 µm Chip thickness 400 µm Seiko epson Corporation S1C17153 TeChniCal Manual (Rev.
  • Page 13 1 OVeRVieW Table 1. 3.1.1 S1C17153 Pad Coordinates name X (µm) Y (µm) name X (µm) Y (µm) 1 P03/EXCL0/LFRO 34 SeG7 -453.5 -896.5 549.0 896.5 2 P04/TOUTA0/CAPA0 35 SeG6 -373.5 -896.5 469.0 896.5 3 P05/TOUTB0/CAPB0/#SPISS0 36 SeG5 -293.5 -896.5 389.0...

  • Page 14: Pin Descriptions

    I/O port pin BZ O Buzzer output pin – I (Pull-up) – P12 I/O I/O port pin #BZ O Buzzer inverted output pin – O (L) – P13 I/O I/O port pin Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 15: Cpu

    2 CPu The S1C17153 contains the S1C17 Core as its core processor. The S1C17 Core is a Seiko Epson original 16-bit RISC-type processor. It features low power consumption, high-speed operation, large address space, main instructions executable in one clock cycle, and a small sized design. The S1C17 Core is suitable for embedded applications such as controllers and sequencers for which an eight-bit CPU is commonly used.

  • Page 16: Cpu Registers

    -[%rb],%rs [%sp+imm7],%rs General-purpose register (16 bits) → stack General-purpose register (16 bits) → memory [imm7],%rs General-purpose register (24 bits) → general-purpose register ld.a %rd,%rs Immediate → general-purpose register (zero-extended) %rd,imm7 Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)
  • Page 17 16-bit comparison with carry between general-purpose registers %rd,%rs cmc/c Supports conditional execution (/c: executed if C = 1, /nc: executed if C = 0). cmc/nc %rd,sign7 16-bit comparison of general-purpose register and immediate with carry Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)
  • Page 18 Delayed call possible calla.d Return from subroutine Delayed return possible ret.d Software interrupt imm5 intl imm5,imm3 Software interrupt with interrupt level setting reti Return from interrupt handling Delayed call possible reti.d Debug interrupt Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 19: Reading Psr

    Reading PSR The S1C17153 includes the MISC_PSR register for reading the contents of the PSR (Processor Status Register) in the S1C17 Core. Reading the contents of this register makes it possible to check the contents of the PSR using the application software.

  • Page 20: Processor Information

    The value of the PSR N (negative) flag can be read out. 1 (R): 0 (R): 0 (default) Processor information The S1C17153 has the IDIR register shown below that allows the application software to identify CPU core type. Processor iD Register (iDiR) Register name address name Function Setting init.

  • Page 21: Memory Map, Bus Control

    3 MeMORY MaP, BuS COnTROl Memory Map, Bus Control Figure 3.1 shows the S1C17153 memory map. 0xff ffff Reserved for core I/O area Peripheral function (Device size) (1K bytes) reserved – 0x56e0–0x5fff 0xff fc00 Real-time clock (16 bits) 0xff fbff 0x56c0–0x56df...

  • Page 22: Restrictions On Access Size

    An instruction fetch and a data access are not performed simultaneously under one of the conditions listed below. This prolongs the instruction fetch cycle for the number of data area bus cycles. • When the S1C17153 executes the instruction stored in the internal ROM area and accesses data in the internal ROM area •...

  • Page 23: Internal Ram Area

    3.3.1 embedded RaM The S1C17153 contains a RAM in the 2K-byte area from address 0x0 to address 0x7ff. The RAM allows high- speed execution of the instruction codes copied into it as well as storing variables and other data. Display RaM area The display RAM for the on-chip LCD driver is located in the 32-byte area beginning with address 0x53c0 in the internal peripheral area.

  • Page 24: S1C17 Core I/O Area

    See “Processor Information” in the “CPU” chapter for more information on IDIR. This area includes the S1C17 Core registers, in addition to those described above. For more information on these registers, refer to the “S1C17 Core Manual.” Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 25: Power Supply

    Do not leave any power supply pins open and be sure to connect them to + power source and GND. internal Power Supply Circuit The S1C17153 has a built-in power supply circuit shown in Figure 4.3.1 to generate the operating voltages required for the internal circuits. I/O interface...

  • Page 26: Heavy Load Protection Mode

    In order to ensure a stable circuit behavior and LCD display quality even if the power supply voltage fluctuates due to driving an external load, the regulators have a heavy load protection function. The table below lists the control bits used for setting heavy load protection mode. Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 27: Control Register Details

    Table 4. 3.2 Clock Division Ratio Selection Division ratio lCDBClKD[2:0] Clock source = OSC3B Clock source = OSC1a Reserved 1/4096 Reserved 1/2048 1/1024 1/512 1/64 1/256 1/32 1/128 1/16 1/64 (Default: 0x0) Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 28: Lcd Voltage Regulator Control Register (Lcd_Vreg)

    2.2 V or less. • Although the reference voltage can be set to V even if V is 2.2 V or higher, current consumption will be increased in comparison with V Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 29: D1 Control Register (Vd1_Ctl)

    Use the heavy load protection function when a heavy load such as a lamp or buzzer is driven with a port output. Current consumption increases in heavy load protection mode, therefore do not set if un- necessary. D[4:0] Reserved Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 30: Initial Reset

    #ReSeT Pin By setting the #RESET pin to low level, the S1C17153 enters initial reset state. In order to initialize the S1C17153 for sure, the #RESET pin must be held at low for more than the prescribed time (see “Input/Output Pin Characteris- tics”...

  • Page 31: Initial Reset Sequence

    The internal peripheral modules are initialized to the default values (except some undefined registers). Change the settings with software if necessary. For the default values set at initial reset, see the list of I/O registers in Appendix or descriptions for each peripheral module. Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 32: Interrupt Controller (Itc)

    Peripheral module Interrupt Interrupt flag Cause of interrupt 1 request Interrupt enable Interrupt level Interrupt flag Vector number Cause of interrupt n Interrupt enable Watchdog timer Reset signal Figure 6. 1.1 Interrupt System Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 33: Vector Table

    *2 Either reset or NMI can be selected as the watchdog timer interrupt with software. Vector numbers 4, 7, 8, 10, 11, 14, 16, and 18 are assigned to the maskable interrupts supported by the S1C17153. Vector table base address The S1C17153 allows the base (starting) address of the vector table to be set using the MISC_TTBRL and MISC_TTBRH registers.

  • Page 34: Vector Table Address Low/High Registers (Misc_Ttbrl, Misc_Ttbrh)

    The previously occurring interrupt is held. The held interrupt is canceled and no interrupt is generated if the interrupt flag in the peripheral module is reset with software. Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 35: Interrupt Processing By The S1C17 Core

    The program resumes processing following the instruction being executed at the time the interrupt oc- curred. In the S1C17153, the watchdog timer can generate a non-maskable interrupt (NMI). The vector number for NMI is 2, with the vector address set to the vector table's starting address + 8 bytes.

  • Page 36: Halt And Sleep Mode Cancellation

    If multiple interrupt requests with the same interrupt level occur simultaneously, the interrupt with the lowest vector number is processed first. The other interrupts are held until all interrupts of higher priority have been accepted by the S1C17 Core. Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)
  • Page 37 16-bit PWM timer Ch.0 interrupt ITC_LV5(0x4310) ILV10[2:0] (D[2:0]) 8-bit timer Ch.0 interrupt (ILV11[2:0] (D[10:8])) Reserved ITC_LV6(0x4312) ILV12[2:0] (D[2:0]) UART Ch.0 interrupt (ILV13[2:0] (D[10:8])) Reserved ITC_LV7(0x4314) ILV14[2:0] (D[2:0]) SPI Ch.0 interrupt (ILV15[2:0] (D[10:8])) Reserved Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 38: Clock Generator (Clg)

    1.1 CLG Module Configuration To reduce current consumption, control the clock in conjunction with processing and use HALT and SLEEP modes. For more information on reducing current consumption, see “Power Saving” in the appendix chapter. Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 39: Clg Input/Output Pins

    After an initial reset, OSC3BEN is set to 1, and the OSC3B oscillator goes on. Since the OSC3B clock is used as the system clock, the S1C17 Core starts operating using the OSC3B clock. Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 40: Osc1A Oscillator

    16-bit PWM timer) and an operation clock for the UART, sound generator, and LCD driver. It can be used as the system clock instead of the OSC3B clock to reduce power consumption when no high-speed processing is required. Figure 7.3.2.1 shows the OSC1A oscillator configuration. Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)
  • Page 41 3.2.3 OSC1A Oscillation Stabilization Wait Time Settings OSC1aWT[1:0] Oscillation stabilization wait time Reserved 4096 cycles Reserved 16384 cycles (Default: 0x0) This is set to 16384 cycles (OSC1A clock) after an initial reset. Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 42: System Clock Switching

    4.1 System Clock Selector The S1C17153 has two system clock sources (OSC3B and OSC1A) and it start operating with the OSC3B clock after an initial reset. The system clock can be switched to the OSC3B clock when a high-speed clock is required for the processing, or to the OSC1A clock for power saving.

  • Page 43: Cpu Core Clock (Cclk) Control

    6.1 Peripheral Module Clock Control Circuit Clock supply control PCLK supply is controlled by PCKEN[1:0]/CLG_PCLK register. Table 7. 6.1 PCLK Control PCKen[1:0] PClK supply Enabled (on) Setting prohibited Setting prohibited Disabled (off) (Default: 0x3) Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 44: Clock External Output (Fouta, Foutb)

    The clock source can be selected from OSC3B and OSC1A using FOUTASRC[1:0]/CLG_FOUTA register or FOUTBSRC[1:0]/CLG_FOUTB register. Table 7. 7.1 Clock Source Selection FOuTaSRC[1:0]/FOuTBSRC[1:0] Clock source 0x3, 0x2 Reserved OSC1A OSC3B (Default: 0x0) Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 45: Control Register Details

    500 kHz 1 MHz 2 MHz D5–2 – reserved – – – 0 when being read. D1–0 ClKSRC[1:0] System clock source select CLKSRC[1:0] Clock source 0x0 R/W 0x3, 0x2 reserved OSC1A OSC3B Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 46: Oscillation Control Register (Clg_Ctl)

    The OSC3B oscillator cannot be stopped if the OSC3B clock is being used as the system clock. OSC1en: OSC1a enable Bit Enables or disables OSC1A oscillator operations. 1 (R/W): Enabled (on) 0 (R/W): Disabled (off) (default) Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 47: Fouta Control Register (Clg_Fouta)

    Enables or disables FOUTA clock external output. 1 (R/W): Enabled (on) 0 (R/W): Disabled (off) (default) Setting FOUTAE to 1 outputs the FOUTA clock from the FOUTA pin. Setting it to 0 stops the output. Seiko epson Corporation 7-10 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 48: Foutb Control Register (Clg_Foutb)

    64 cycles D5–2 – reserved – – – 0 when being read. D1–0 OSC1aWT OSC1A stabilization wait cycle OSC1AWT[1:0] Wait cycle 0x0 R/W [1:0] select reserved 4096 cycles reserved 16384 cycles Seiko epson Corporation S1C17153 TeChniCal Manual 7-11 (Rev. 1.0)

  • Page 49: Pclk Control Register (Clg_Pclk)

    D7–2 – reserved – – – 0 when being read. Register (8 bits) D1–0 PCKen[1:0] PCLK enable PCKEN[1:0] PCLK supply 0x3 R/W (ClG_PClK) Enable Not allowed Not allowed Disable D[7:2] Reserved Seiko epson Corporation 7-12 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 50: Cclk Control Register (Clg_Cclk)

    Selects the gear ratio for reducing system clock speed and sets the CCLK clock speed for operating the S1C17 Core. To reduce current consumption, operate the S1C17 Core using the slowest possible clock speed. Seiko epson Corporation S1C17153 TeChniCal Manual 7-13 (Rev. 1.0)
  • Page 51 7 ClOCK GeneRaTOR (ClG) Table 7. 8.11 CCLK Gear Ratio Selection CClKGR[1:0] Gear ratio (Default: 0x0) Seiko epson Corporation 7-14 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 52: Real-Time Clock (Rtc)

    8 Real-TiMe ClOCK (RTC) Real-Time Clock (RTC) RTC Module Overview The S1C17153 incorporates a real-time clock (RTC). The main features of the RTC are outlined below. • Contains time counters (seconds, minutes, and hours). • The RTC operates with the OSC1A oscillator circuit even in SLEEP mode.
  • Page 53 22 o'clock (10pm) 0x16 0x22 0x10 23 o'clock (11pm) 0x17 0x23 0x11 initial counter values An initial reset does not initialize the counter values. Be sure to initialize the counters via software. Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 54: Rtc Control

    2. Wait until RTCST/RTC_CTL register is reset to 0 (the RTC actually stops operating). 3. Write the counter values to the RTC_MS and RTC_H registers. 4. Start the RTC by writing 1 to RTCRUN/RTC_CTL register. Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 55: Counter Read

    Current time = A (B) Figure 8. 3.5.1 Procedure for Reading Counters Read procedure 2 After a 1 Hz interrupt (or 10-second to 1 day interrupt) occurs, read the RTC_MS and RTC_H registers within one second. Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 56: Rtc Interrupts

    1 BCD mode 0 Binary mode RTC24h 24H/12H mode select 1 12H 0 24H D3–1 – reserved – – – 0 when being read. RTCRun RTC run/stop control 1 Run 0 Stop D[15:9] Reserved Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 57: Rtc Interrupt Enable Register (Rtc_Ien)

    1, the corresponding interrupt flag will be set to 1 in the interrupt cycles and the interrupt request will be sent to the ITC. If an interrupt enable bit is set to 0, the interrupt request will not be sent to the ITC. 1 (R/W): Interrupt enabled 0 (R/W): Interrupt disabled (default) D[15:10] Reserved Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 58: Rtc Interrupt Flag Register (Rtc_Iflg)

    Indicates half-day interrupt cause occurrence status. INTHD is set to 1 at the same time the hour counter changes from 11 to 12, 23 to 0 (in 24-hour mode), or 11am to 12pm, 11pm to 12am (in 12-hour mode). Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 59: Rtc Minute/Second Counter Register (Rtc_Ms)

    • For the counter read and write procedures, see Section 8.3.5, “Counter Read,” and Section 8.3.4, “Counter Settings.” • Do not set the counters while the RTC is running, as proper settings to the counters cannot be guaranteed. Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 60: Rtc Hour Counter Register (Rtc_H)

    • Counter values to be set must be within the effective range according to binary/BCD mode. The counter will be undefined if a value out of the range is written. • Depending on the value set, an interrupt may occur immediately after starting the RTC. Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 61: I/O Ports (P)

    • The “xy” in the register and bit names refers to the port number (Pxy, x = 0 and 1, y = 0 to 7). Example: PxINy/Px_IN register P00: P0IN0/P0_IN register P13: P1IN3/P1_IN register Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 62: Input/Output Pin Function Selection (Port Mux)

    Output and input are both disabled. The value read from PxINy (input data) is 0. The input/output direction of ports with a peripheral module function selected is controlled by the peripheral module. PxOENy and PxIENy settings are ignored. Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 63: Pull-Up Control

    Figure 9.5.1 shows the port input interrupt circuit configuration. Chattering filter Interrupt flag P0CF1[2:0] P0IF0 Interrupt edge selection P0EDGE0 Interrupt enable P0IE0 P0 port interrupt request (to ITC) P0CF2[2:0] P0IF7 P0EDGE7 P0IE7 Figure 9. 5.1 Port Input Interrupt Circuit Configuration Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 64: P0 Port Chattering Filter Function

    P0 port interrupt. Also the chatter- ing filter circuit requires a maximum of twice the check time for stabilizing the operation status. Before enabling the interrupt, make sure that the stabilization time has elapsed. Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 65: P0 Port Key-Entry Reset

    P1IN[3:0] only are available for the P1 ports. Other bits are reserved and always read as 0. D[7:0] Pxin[7:0]: Px[7:0] Port input Data Bits The port pin status can be read out. (Default: external input status) 1 (R): High level 0 (R): Low level Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 66: Px Port Output Data Registers (Px_Out)

    P1PU[3:0] only are available for the P1 ports. Other bits are reserved and always read as 0. D[7:0] PxPu[7:0]: Px[7:0] Port Pull-up enable Bits Enables or disables the pull-up resistor included in each port. 1 (R/W): Enabled (default) 0 (R/W): Disabled Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 67: P0 Port Interrupt Mask Register (P0_Imsk)

    1, a port interrupt request signal is also output to the ITC at the same time. An interrupt is generated if the ITC and S1C17 Core interrupt conditions are satisfied. Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 68: P0 Port Chattering Filter Control Register (P0_Chat)

    CPU into SLEEP status. • The chattering filter check time refers to the maximum pulse width that can be filtered. Gen- erating an input interrupt requires an input time of twice the check time. Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 69: P0 Port Key-Entry Reset Configuration Register (P0_Krst)

    Px_IN register. Setting to 0 disables input. Refer to Table 9.3.1 for more information on port input/output status, including settings other than for the Px_IEN register. Seiko epson Corporation S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 70: P0[3:0] Port Function Select Register (P00_03Pmux)

    0x1 (R/W): SOUT0 (UART) 0x0 (R/W): P01 port (default) D[1:0] P00MuX[1:0]: P00 Port Function Select Bits 0x3 (R/W): Reserved 0x2 (R/W): Reserved 0x1 (R/W): SIN0 (UART) 0x0 (R/W): P00 port (default) Seiko epson Corporation 9-10 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 71: P0[7:4] Port Function Select Register (P04_07Pmux)

    D[1:0] P04MuX[1:0]: P04 Port Function Select Bits 0x3 (R/W): Reserved 0x2 (R/W): Reserved 0x1 (R/W): TOUTA0 (T16A2 Ch.0 comparator mode) or CAPA0 (T16A2 Ch.0 capture mode) 0x0 (R/W): P04 port (default) Seiko epson Corporation S1C17153 TeChniCal Manual 9-11 (Rev. 1.0)

  • Page 72: P1[3:0] Port Function Select Register (P10_13Pmux)

    0x1 (R/W): P11 port 0x0 (R/W): Reserved (default) D[1:0] P10MuX[1:0]: P10 Port Function Select Bits 0x3 (R/W): Reserved 0x2 (R/W): SPICLK0 (SPI Ch.0) 0x1 (R/W): FOUTB (CLG) 0x0 (R/W): P10 port (default) Seiko epson Corporation 9-12 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 73: 10 8-Bit Timer (T8)

    8-bit Timer (T8) 10.1 T8 Module Overview The S1C17153 includes an 8-bit timer module (T8). The features of the T8 module are listed below. • Consists of one timer channel (T8 Ch.0). • 8-bit presettable down counter with an 8-bit reload data register for setting the preset value •...

  • Page 74: Count Clock

    (or between underflows). The time determined is used to obtain the specified wait time, the intervals between periodic interrupts, and the programmable serial interface transfer clock. Seiko epson Corporation 10-2 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 75: Timer Reset

    Write 0 to PRUN to stop the timer via the application program. The counter stops counting and retains the current counter value until either the timer is reset or restarted. To restart the count from the initial value, the timer should be reset before writing 1 to PRUN. Seiko epson Corporation S1C17153 TeChniCal Manual 10-3 (Rev. 1.0)

  • Page 76: T8 Output Signals

    • The T8 module interrupt flag T8IF must be reset in the interrupt handler routine after a T8 in- terrupt has occurred to prevent recurring interrupts. • Reset T8IF before enabling T8 interrupts with T8IE to prevent occurrence of unwanted inter- rupt. T8IF is reset by writing 1. Seiko epson Corporation 10-4 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 77: Control Register Details

    The reload data set in this register is preset to the counter when the timer is reset or the counter under- flows. If the timer is started after resetting, it counts down from the reload value (initial value). Seiko epson Corporation S1C17153 TeChniCal Manual 10-5 (Rev. 1.0)

  • Page 78: T8 Ch.x Counter Data Register (T8_Tcx)

    The timer starts counting when PRUN is written as 1 and stops when written as 0. When the timer is stopped, the counter data is retained until reset or until the next RUN state. Seiko epson Corporation 10-6 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 79: T8 Ch.x Interrupt Control Register (T8_Intx)

    No cause of interrupt has occurred (default) 1 (W): Flag is reset 0 (W): Ignored T8IF is the T8 module interrupt flag that is set to 1 when the counter underflows. T8IF is reset by writing 1. Seiko epson Corporation S1C17153 TeChniCal Manual 10-7 (Rev. 1.0)

  • Page 80: 16-Bit Pwm Timer (T16A2)

    11.1 T16a2 Module Overview The S1C17153 includes a 16-bit PWM timer (T16A2) module that consists of counter blocks and comparator/ capture blocks. This timer can be used as an interval timer, PWM waveform generator, external event counter and a count capture unit to measure external event periods.

  • Page 81: T16A2 Input/Output Pins

    The clock controller includes a clock source selector, dividers, and a gate circuit for controlling the count clock. T16ACLKD[3:0] T16ACLKSRC[1:0] Divider OSC3B clock (1/1–1/16K) Divider OSC1A clock (1/1–1/256) Counter Ch.x T16ACLKE External clock (EXCLx) Clock controller Ch.x Figure 11. 3.1 Clock Controller Seiko epson Corporation 11-2 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 82: T16A2 Operating Modes

    Make sure the T16A2 count is stopped before setting the count clock. 11.4 T16a2 Operating Modes The T16A2 module provides some operating modes to support various usages. This section describes the functions of each operating mode and how to enter the mode. Seiko epson Corporation S1C17153 TeChniCal Manual 11-3 (Rev. 1.0)

  • Page 83: Comparator Mode And Capture Mode

    Channel Capture a Capture B T16A2 Ch.0 CAPA0 CAPB0 The trigger edge of the signal can be selected using the CAPATRG[1:0]/T16A_CCCTLx register for capture A and CAPBTRG[1:0]/T16A_CCCTLx register for capture B. Seiko epson Corporation 11-4 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 84: Repeat Mode And One-Shot Mode

    Use HCM/T16A_CTLx register to select half clock mode. normal clock mode (hCM = 0, default) In normal clock mode, T16A2 generates a compare A signal when the T16A_TCx register value matches the T16A_CCAx register. Seiko epson Corporation S1C17153 TeChniCal Manual 11-5 (Rev. 1.0)

  • Page 85: Counter Control

    16-bit transfer instruction. If data is read twice using an 8-bit trans- fer instruction, the correct value may not be obtained due to occurrence of count up between readings. Seiko epson Corporation 11-6 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 86: Counter Operation And Interrupt Timing Charts

    T16A2 includes two TOUT output circuits and their signal generation and output can be controlled individually. Al- though the output circuit and register names use letters ‘A’ and ‘B’ to distinguish two systems, it does not mean that they correspond to compare A and B signals. Seiko epson Corporation S1C17153 TeChniCal Manual 11-7 (Rev. 1.0)
  • Page 87 (TOUTAMD[1:0] = 0x2, TOUTAINV = 1) (TOUTAMD[1:0] = 0x3, TOUTAINV = 0) (TOUTAMD[1:0] = 0x3, TOUTAINV = 1) (When T16A_CCAx = 3, T16A_CCBx = 5) Figure 11. 6.2 TOUT Output Waveform Seiko epson Corporation 11-8 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 88: T16A2 Interrupts

    The T16A2 module outputs a single interrupt signal shared by the above interrupt causes to the interrupt controller (ITC). Read the interrupt flags in the T16A2 module to identify the interrupt cause that has been occurred. Seiko epson Corporation S1C17153 TeChniCal Manual 11-9 (Rev. 1.0)
  • Page 89 ITC. An interrupt is generated if the ITC and S1C17 core interrupt conditions are satisfied. For more information on interrupt control registers and the operation when an interrupt occurs, see the “Interrupt Controller (ITC)” chapter. Seiko epson Corporation 11-10 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 90: Control Register Details

    T16aClKe Count clock enable 1 Enable 0 Disable D[7:4] T16aClKD[3:0]: Clock Division Ratio Select Bits Selects the division ratio for generating the count clock when an internal clock (OSC3B or OSC1A) is used. Seiko epson Corporation S1C17153 TeChniCal Manual 11-11 (Rev. 1.0)

  • Page 91: T16A Counter Ch.x Control Register (T16A_Ctlx)

    A signal when the dual-edge counter value matches the T16A_CCAx register. This makes it possible to control the duty ratio with double accuracy as compared to normal clock mode. Seiko epson Corporation 11-12 S1C17153 TeChniCal Manual (Rev. 1.0)
  • Page 92 0 (R): Stopped (default) The counter starts counting when PRUN is written as 1 and stops when written as 0. The counter data is retained even if the counter is stopped. Seiko epson Corporation S1C17153 TeChniCal Manual 11-13 (Rev. 1.0)

  • Page 93: T16A Counter Ch.x Data Register (T16A_Tcx)

    B signals. These bits are also used to turn the TOUT B output On and Off. Table 11. 8.5 TOUT B Generation Mode TOuTBMD[1:0] When compare a occurs When compare B occurs No change Toggle Toggle No change Rise Fall Disable output (Default: 0x0) Seiko epson Corporation 11-14 S1C17153 TeChniCal Manual (Rev. 1.0)
  • Page 94 Writing 1 to TOUTAINV generates an active Low signal (Off level = High) for the TOUT A output. When TOUTAINV is 0, an active High signal (Off level = Low) is generated. TOUTAINV is a control bit for comparator mode and is ineffective in capture mode. Seiko epson Corporation S1C17153 TeChniCal Manual 11-15 (Rev. 1.0)

  • Page 95: T16A Comparator/Capture Ch.x A Data Register (T16A_Ccax)

    B signal is asserted and a cause of compare B interrupt occurs. The counter is reset to 0. Furthermore, the TOUT output waveform changes when TOUTAMD[1:0]/T16A_CCCTLx register or TOUTBMD[1:0]/T16A_CCCTLx register is set to 0x3 or 0x1. Seiko epson Corporation 11-16 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 96: T16A Comparator/Capture Ch.x Interrupt Enable Register (T16A_Ienx)

    Enables or disables compare A interrupts. 1 (R/W): Interrupt enabled 0 (R/W): Interrupt disabled (default) Setting CAIE to 1 enables compare A interrupt requests to the ITC. Setting it to 0 disables interrupts. Seiko epson Corporation S1C17153 TeChniCal Manual 11-17 (Rev. 1.0)

  • Page 97: T16A Comparator/Capture Ch.x Interrupt Flag Register (T16A_Iflgx)

    Indicates whether the cause of compare B interrupt has occurred or not. 1 (R): Cause of interrupt has occurred 0 (R): No cause of interrupt has occurred (default) 1 (W): Flag is reset 0 (W): Ignored Seiko epson Corporation 11-18 S1C17153 TeChniCal Manual (Rev. 1.0)
  • Page 98 0 (W): Ignored CAIF is a T16A2 interrupt flag that is set to 1 when the counter reaches the value set in the compare A register. CAIF is reset by writing 1. Seiko epson Corporation S1C17153 TeChniCal Manual 11-19 (Rev. 1.0)

  • Page 99: Clock Timer (Ct)

    12.1 CT Module Overview The S1C17153 includes a clock timer module (CT) that uses the OSC1A oscillator as its clock source. This timer can be used for generating cyclic interrupts to implement a software clock function. The features of the CT module are listed below.

  • Page 100: Timer Run/Stop Control

    The CT module outputs a single interrupt signal shared by the above four interrupt causes to the interrupt controller (ITC). The interrupt flag in the CT module should be read to identify the cause of interrupt that occurred. Seiko epson Corporation 12-2 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 101: Control Register Details

    The clock timer starts counting when CTRUN is written as 1 and stops when written as 0. The counter data is retained at Stop state until a reset or the next Run state. Seiko epson Corporation S1C17153 TeChniCal Manual 12-3 (Rev. 1.0)

  • Page 102: Clock Timer Counter Register (Ct_Cnt)

    1 at the falling edge of the corresponding 32 Hz, 8 Hz, 2 Hz, or 1 Hz interrupt. CTIF* is reset by writing 1. Seiko epson Corporation 12-4 S1C17153 TeChniCal Manual (Rev. 1.0)
  • Page 103 Indicates whether the cause of 1 Hz interrupt has occurred or not. 1 (R): Cause of interrupt has occurred 0 (R): No cause of interrupt has occurred (default) 1 (W): Flag is reset 0 (W): Ignored Seiko epson Corporation S1C17153 TeChniCal Manual 12-5 (Rev. 1.0)

  • Page 104: Watchdog Timer (Wdt)

    Watchdog Timer (WDT) 13.1 WDT Module Overview The S1C17153 includes a watchdog timer module (WDT) that uses the OSC1A oscillator as its clock source. This timer is used to detect CPU runaway. The features of WDT are listed below. • 10-bit up counter •...

  • Page 105: Wdt Run/Stop Control

    0 when being read. Timer Control (8 bits) WDTRST Watchdog timer reset 1 Reset 0 Ignored Register D3–0 WDTRun[3:0] Watchdog timer run/stop control Other than 1010 1010 1010 R/W (WDT_CTl) Stop D[7:5] Reserved Seiko epson Corporation 13-2 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 106: Watchdog Timer Status Register (Wdt_St)

    This bit confirms that WDT was the source of the NMI. The WDTST set to 1 is cleared to 0 by resetting WDT. This is also set by a counter overflow if reset output is selected, but is cleared by initial reset and cannot be confirmed. Seiko epson Corporation S1C17153 TeChniCal Manual 13-3 (Rev. 1.0)

  • Page 107: Uart

    14.1 uaRT Module Overview The S1C17153 includes a UART module for asynchronous communication. It includes a 2-byte receive data buffer and 1-byte transmit data buffer allowing successive data transfer. The UART module also includes an RZI modula- tor/demodulator circuit that enables IrDA 1.0-compatible infrared communications simply by adding basic external circuits.

  • Page 108: Uart Input/Output Pins

    When inputting the external clock via the SCLKx pin, the clock duty ratio must be 50%. When OSC3B is selected as the clock source, use UTCLKD[1:0]/UART_CLKx register to select the division ratio. Seiko epson Corporation 14-2 S1C17153 TeChniCal Manual (Rev. 1.0)
  • Page 109 – – – – – – – – – – – – – – – – – – – – – – – D: Indicates the insertion of a delay cycle. Seiko epson Corporation S1C17153 TeChniCal Manual 14-3 (Rev. 1.0)

  • Page 110: Transfer Data Settings

    CHLN = 1, PREN = 0, STPB = 1 CHLN = 1, PREN = 1, STPB = 1 s1: start bit, s2 & s3: stop bit, p: parity bit Figure 14.4.1 Transfer Data Format Seiko epson Corporation 14-4 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 111: Data Transfer Control

    End of transmission interrupt request Transmit buffer empty interrupt request S1: Start bit, S2: Stop bit, P: Parity bit, Wr: Data write to transmit data buffer Figure 14. 5.1 Data Transmission Timing Chart Seiko epson Corporation S1C17153 TeChniCal Manual 14-5 (Rev. 1.0)
  • Page 112 RBFI/UART_CTLx register to 1 so that an interrupt occurs when the receive data buffer receives two 8-bit data. Three error flags are also provided in addition to the flags previously mentioned. See Section 14.6 for detailed information on flags and receive errors. Seiko epson Corporation 14-6 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 113: Receive Errors

    If an overrun error occurs, the overrun error flag OER/UART_STx register is set to 1. The receiving operation continues even if this error occurs. The OER flag is reset to 0 by writing 1. Seiko epson Corporation S1C17153 TeChniCal Manual 14-7 (Rev. 1.0)

  • Page 114: Uart Interrupts

    UART interrupt handler routine to determine whether the UART interrupt was caused by a receive error. If any of the error flags has the value 1, the interrupt handler routine will proceed with error recovery. For more information on interrupt processing, see the “Interrupt Controller (ITC)” chapter. Seiko epson Corporation 14-8 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 115: Irda Interface

    Data transfer control in IrDA mode is identical to that for normal interfaces. For detailed information on data format settings and data transfer and interrupt control methods, refer to the preceding sections. Seiko epson Corporation S1C17153 TeChniCal Manual 14-9 (Rev. 1.0)

  • Page 116: Control Register Details

    Ignored FER is set to 1 when a framing error occurs. Framing errors occur when data is received with the stop bit set to 0. FER is reset by writing 1. Seiko epson Corporation 14-10 S1C17153 TeChniCal Manual (Rev. 1.0)
  • Page 117 Data exists TDBE is reset to 0 when transmit data is written to the transmit data buffer and is set to 1 when the data is transferred to the shift register. Seiko epson Corporation S1C17153 TeChniCal Manual 14-11 (Rev. 1.0)

  • Page 118: Uart Ch.x Transmit Data Register (Uart_Txdx)

    – reserved – – – 0 when being read. D[7:5] Reserved Chln: Character length Select Bit Selects the serial transfer data length. 1 (R/W): 8 bits 0 (R/W): 7 bits (default) Seiko epson Corporation 14-12 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 119: Uart Ch.x Control Register (Uart_Ctlx)

    (i.e. when data transmission begins). 1 (R/W): Enabled 0 (R/W): Disabled (default) Set this bit to 1 to write data to the transmit data buffer using interrupts. Seiko epson Corporation S1C17153 TeChniCal Manual 14-13 (Rev. 1.0)

  • Page 120: Uart Ch.x Expansion Register (Uart_Expx)

    ÷ 16 BR = ——— - FMD - 16 ct_clk: Count clock frequency (Hz) BR[7:0] setting (0 to 255) bps: Transfer rate (bit/s) FMD: FMD[3:0] (fine mode) setting (0 to 15) Seiko epson Corporation 14-14 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 121: Uart Ch.x Fine Mode Register (Uart_Fmdx)

    UTCLKSRC 0x0 R/W Clock source [1:0] [1:0] External clock reserved OSC1A OSC3B – reserved – – – 0 when being read. uTClKe Count clock enable 1 Enable 0 Disable D[7:6] Reserved Seiko epson Corporation S1C17153 TeChniCal Manual 14-15 (Rev. 1.0)
  • Page 122 1 (R/W): Enabled (on) 0 (R/W): Disabled (off) (default) The UTCLKE default setting is 0, which disables the clock supply. Setting UTCLKE to 1 sends the clock selected to the counter. Seiko epson Corporation 14-16 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 123: Spi

    15 SPi 15.1 SPi Module Overview The S1C17153 includes a synchronized serial interface module (SPI). The following shows the main features of the SPI: • Number of channels: 1 channel • Supports both master and slave modes. • Data length: 8 bits fixed •...

  • Page 124: Spi Clock

    The SPI clock polarity is selected by CPOL/SPI_CTLx register. Setting CPOL to 1 treats the SPI clock as ac- tive Low; setting it to 0 (default) treats it as active High. The SPI clock phase is selected by CPHA/SPI_CTLx register. As shown below, these control bits set transfer timing. Seiko epson Corporation 15-2 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 125: Data Transfer Control

    In slave mode, SPBSY flag indicates the SPI slave selection signal (#SPISSx pin) status. The flag is set to 1 when the SPI module is selected as a slave module and is set to 0 when the module is not selected. Seiko epson Corporation S1C17153 TeChniCal Manual 15-3 (Rev. 1.0)
  • Page 126 In master mode, the SPBSY flag indicating the shift register status can be used in the same way while transfer- ring data. Seiko epson Corporation 15-4 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 127: Spi Interrupts

    SPI interrupt is attributable to a receive buffer full. If SPRBF is 1, the received data can be read from the receive data buffer by the interrupt handler routine. For more information on interrupt processing, see the “Interrupt Controller (ITC)” chapter. Seiko epson Corporation S1C17153 TeChniCal Manual 15-5 (Rev. 1.0)

  • Page 128: Control Register Details

    SPTBE is set to 0 when transmit data is written to the SPI_TXDx register (transmit data buffer), and is set to 1 when the data is transferred to the shift register (when transmission starts). Transmission data must be written to the SPI_TXDx register when this bit is 1. Seiko epson Corporation 15-6 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 129: Spi Ch.x Transmit Data Register (Spi_Txdx)

    0 Disable note: Do not access to the SPI_CTLx register while SPBSY/SPI_STx register is set to 1 or SPRBF/ SPI_STx register is set to 1 (while data is being transmitted/received). D[15:10] Reserved Seiko epson Corporation S1C17153 TeChniCal Manual 15-7 (Rev. 1.0)
  • Page 130 Figure 15. 7.1 Clock and Data Transfer Timing MSSl: Master/Slave Mode Select Bit Sets the SPI module to master or slave mode. 1 (R/W): Master mode 0 (R/W): Slave mode (default) Seiko epson Corporation 15-8 S1C17153 TeChniCal Manual (Rev. 1.0)
  • Page 131 Setting SPEN to 1 starts the SPI module operation, enabling data transfer. Setting SPEN to 0 stops the SPI module operation. note: The SPEN bit should be set to 0 before setting the CPHA, CPOL, and MSSL bits. Seiko epson Corporation S1C17153 TeChniCal Manual 15-9 (Rev. 1.0)

  • Page 132: Lcd Driver (Lcd)

    LCD Driver (LCD) 16.1 lCD Module Overview The S1C17153 includes an LCD driver capable of driving an LCD panel with up to 128 segments (32 segments × 4 commons). The main features of the LCD driver are listed below. 32 SEG × 4/3/2/1 COM •...

  • Page 133: Lcd Clock

    If LCLK is not supplied, the LCD cannot display. However, the LCD driver control registers and display mem- ory can be accessed even if LCLK is stopped. note: Be sure to set LCDTCLKE to 0 before selecting a clock division ratio. Seiko epson Corporation 16-2 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 134: Frame Signal

    COM0 to COM1 SEG0 to SEG31 64 segments Static COM0 SEG0 to SEG31 32 segments (Default: 0x3) The drive bias is fixed at 1/3 (three potentials V ) for all duty settings. Seiko epson Corporation S1C17153 TeChniCal Manual 16-3 (Rev. 1.0)

  • Page 135: Drive Waveform

    Figures 16.4.2.1 to 16.4.2.4 shows the drive waveforms according to the duty selections. Frame interrupt Frame interrupt 1 frame LFRO COM0 display status COM1 COM0 COM2 SEGx COM3 SEGx Figure 16. 4.2.1 1/4 Duty Drive Waveform Seiko epson Corporation 16-4 S1C17153 TeChniCal Manual (Rev. 1.0)
  • Page 136 16 lCD DRiVeR (lCD) Frame interrupt Frame interrupt 1 frame LFRO COM0 display status COM0 COM1 SEGx COM2 SEGx Figure 16. 4.2.2 1/3 Duty Drive Waveform Seiko epson Corporation S1C17153 TeChniCal Manual 16-5 (Rev. 1.0)
  • Page 137 COM0 COM0 SEGx COM1 SEGx Figure 16. 4.2.3 1/2 Duty Drive Waveform Frame interrupt Frame interrupt 1 frame display status LFRO COM0 SEGx COM0 SEGx Figure 16. 4.2.4 Static Drive Waveform Seiko epson Corporation 16-6 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 138: Display Memory

    16 lCD DRiVeR (lCD) 16.5 Display Memory The S1C17153 includes a 32-byte display memory (address 0x53c0 to address 0x53df). Figures 16.5.1 to 16.5.4 show the correspondence between display memory and COM/SEG pins for each drive duty. Writing 1 to a display memory bit corresponding to a segment on the LCD panel turns the segment on, while writ- ing 0 turns the segment off.

  • Page 139: Display Control

    Setting DSPREV/LCD_DCTL register to 0 inverts the display; setting to 1 returns the display to normal status. Note that the display will not be inverted if “All off” is selected using DSPC[1:0]. The display will be inverted when “All on” is selected. Seiko epson Corporation 16-8 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 140: Lcd Interrupt

    LCD clock enable 1 Enable 0 Disable D[7:6] Reserved D[5:4] lCDTClKD[1:0]: lCD Clock Division Ratio Select Bits Selects the division ratio when OSC3B is selected as the LCD clock source. Seiko epson Corporation S1C17153 TeChniCal Manual 16-9 (Rev. 1.0)

  • Page 141: Lcd Display Control Register (Lcd_Dctl)

    D[1:0] DSPC[1:0]: lCD Display Control Bits Controls the LCD display. Table 16. 8.4 LCD Display Control DSPC[1:0] lCD display All off (static) All on (dynamic) Normal display Display off (Default: 0x0) Seiko epson Corporation 16-10 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 142: Lcd Clock Control Register (Lcd_Cctl)

    Static (0x0) OSC3B OSC3B OSC3B OSC3B –––––––– –––––––– –––––––– –––––––– –––––––– –––––––– –––––––– –––––––– * Default setting : OSC3B clock frequency OSC3B LCDTCLKD: OSC3B division ratio (1/1024 to 1/8192) D[5:3] Reserved Seiko epson Corporation S1C17153 TeChniCal Manual 16-11 (Rev. 1.0)

  • Page 143: Lcd Voltage Regulator Control Register (Lcd_Vreg)

    No cause of interrupt has occurred (default) 1 (W): Flag is reset 0 (W): Ignored IFRMFLG is set to 1 at the frame signal rising edge. IFRMFLG is reset to 0 by writing 1. Seiko epson Corporation 16-12 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 144: Sound Generator (Snd)

    17.1 SnD Module Overview The S1C17153 includes a sound generator (SND) for generating a buzzer signal. The main features of the SND module are outlined below. • Provides buzzer inverted and non-inverted output pins to directly drive a piezoelectric buzzer.

  • Page 145: Buzzer Frequency And Volume Settings

    Level 7 Level 8 (Min.) Figure 17. 4.2.1 Buzzer Signal Waveforms by Different Duty Ratios note: BZDT[2:0] is ineffective in envelope mode, as the duty ratio is automatically controlled by the hardware. Seiko epson Corporation 17-2 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 146: Buzzer Mode And Output Control

    When the set time has elapsed, the buzzer output stops. BZEN functions as a status bit. It retains 1 while a one-shot buzzer signal is being output and reverts to 0 upon completion of the output. Seiko epson Corporation S1C17153 TeChniCal Manual 17-3 (Rev. 1.0)

  • Page 147: Output Control In Envelope Mode

    Writing 1 to BZEN again before a buzzer output is finished, the duty ratio returns to the maximum level and a new envelope output begins from that point. Figure 17.5.4.1 shows a timing chart in envelope mode. Seiko epson Corporation 17-4 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 148: Control Register Details

    D3–2 BZMD[1:0] Buzzer mode select BZMD[1:0] Mode 0x0 R/W reserved Envelope One-shot Normal – reserved – – – 0 when being read. BZen Buzzer output control 1 On/Trigger 0 Off D[7:6] Reserved Seiko epson Corporation S1C17153 TeChniCal Manual 17-5 (Rev. 1.0)
  • Page 149 BZEN while a buzzer signal is being output stops the output immediately. Writing 1 to BZEN again before a buzzer output is finished, the duty ratio returns to the maximum level and a new envelope output begins from that point. Seiko epson Corporation 17-6 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 150: Buzzer Frequency Control Register (Snd_Bzfq)

    Setting BZDT[2:0] to 0x0 turns the volume up to maximum level; setting it to 0x7 turns the volume down to minimum level. note: BZDT[2:0] is ineffective in envelope mode, as the duty ratio is automatically controlled by the hardware. Seiko epson Corporation S1C17153 TeChniCal Manual 17-7 (Rev. 1.0)

  • Page 151: Supply Voltage Detection Circuit (Svd)

    SVD Module Overview The S1C17153 includes an SVD (supply voltage detection) circuit to monitor the power voltage supplied to the V pin. It can be used to check whether the power supply voltage drops below the detection level set with software or not.

  • Page 152: Svd Control

    SVDEN should be set to 0 after the response time has elapsed. For these response times, see “Electrical Characteristics.” • Operating the SVD circuit increases current consumption. If power supply voltage detection is not required, stop SVD operations by setting SVDEN to 0. Seiko epson Corporation 18-2 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 153: Svd Comparison Voltage Register (Svd_Cmp)

    The comparison voltage is effective only when it is set within the operating voltage range. If the comparison voltage set is out of the operating voltage range, no correct detection results will be obtained. Seiko epson Corporation S1C17153 TeChniCal Manual 18-3 (Rev. 1.0)

  • Page 154: Svd Detection Result Register (Svd_Rslt)

    SVDDT. Also the detection result is set to SVDDT by writing 0 to SVDEN, so the power supply voltage status can be checked by reading SVDDT after that. Seiko epson Corporation 18-4 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 155: Multiplier/Divider (Copro)

    19 MulTiPlieR/DiViDeR (COPRO) Multiplier/Divider (COPRO) 19.1 Overview The S1C17153 has an embedded coprocessor that provides multiplier/divider functions. The following shows the features of the multiplier/divider: • Multiplication: Supports signed/unsigned multiplications. (16 bits × 16 bits = 32 bits) Can be executed in 1 cycle.

  • Page 156: Multiplication

    Argument 2 Argument 1 16 bits 32 bits Operation S1C17 Core result Operation result register Selector Coprocessor output (16 bits) Flag output Figure 19. 3.1 Data Path in Multiplication Mode Seiko epson Corporation 19-2 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 157: Division

    ← %rd ÷ %rs 0x018 ld.ca %rd,%rs %rd ← res[31:16] (residue) or 0x19 res[31:0] ← %rd ÷ imm7/16 (ext imm9) %rd ← res[31:16] (residue) ld.ca %rd,imm7 res: operation result register Seiko epson Corporation S1C17153 TeChniCal Manual 19-3 (Rev. 1.0)

  • Page 158: Mac

    When repeating the MAC operation without operation result read mode inserted, send multiplicand and multiplier data for number of required times. In this case it is not necessary to set the MAC mode every time. Seiko epson Corporation 19-4 S1C17153 TeChniCal Manual (Rev. 1.0)
  • Page 159 The overflow (V) flag that has been set will be cleared when an overflow has not been occurred during execu- tion of the “ld.ca” instruction for MAC operation or when the “ld.ca” or “ld.cf” instruction is executed in an operation mode other than operation result read mode. Seiko epson Corporation S1C17153 TeChniCal Manual 19-5 (Rev. 1.0)

  • Page 160: Reading Operation Results

    (CVZN) ← 0b0000 This operation mode does not 0x03 ld.ca %rd,%rs affect the operation result reg- ld.ca %rd,imm7 %rd ← res[15:0] ister. %rd ← res[31:16] 0x13 ld.ca %rd,%rs ld.ca %rd,imm7 %rd ← res[31:16] res: operation result register Seiko epson Corporation 19-6 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 161: Electrical Characteristics

    *1 The values of current consumption during execution were measured when a test program consisting of 60.5% ALU instructions, 17% branch instructions, 12% memory read instructions, and 10.5% memory write instructions was executed continuously in the ROM. Seiko epson Corporation S1C17153 TeChniCal Manual 20-1 (Rev. 1.0)
  • Page 162 Gear ratio Gear ratio Ta [°C] Ta [°C] Current consumption-frequency characteristic during execution with OSC3B OSC3B = ON, OSC1A = 32.768kHz crystal, PCKEN[1:0] = 0x3, Ta = 25°C, Typ. value [MHz] OSC3B Seiko epson Corporation 20-2 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 163: Oscillation Characteristics

    – – Built-in gate capacitance – – Built-in drain capacitance *1 Crystal resonator = C-002RX: manufactured by SEIKO EPSON (R = 50kW Max., C = 7pF) OSC3B oscillation Unless otherwise specified: V = 2.0 to 3.6V, V = 0V, Ta = 25°C...
  • Page 164 #RESET Cres #RESET 0.5V 0.1V Power on note: Be sure to set the #RESET pin to 0.1 V or less when performing a power-on reset after the power is turned off. Seiko epson Corporation 20-4 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 165: Spi Characteristics

    Connect 1MW load resistor between V and V 0.977 Typ. × Typ. × reference voltage) Connect 1MW load resistor between V and V 1.884 0.96 1.04 Connect 1MW load resistor between V and V 2.800 Seiko epson Corporation S1C17153 TeChniCal Manual 20-5 (Rev. 1.0)
  • Page 166 = 0V, Ta = -40 to 85°C item Symbol Condition Min. Typ. Max. unit Segment/Common output current SEGxx, COMxx, V - 0.1V – – µA SEGH SEGH SEGxx, COMxx, V = 0.1V – – µA SEGL SEGL Seiko epson Corporation 20-6 S1C17153 TeChniCal Manual (Rev. 1.0)
  • Page 167 When a 1 MW load resistor is connected between V –V and V –V and a 1µA load is connected to V reference) Current consumption characteristic Drive voltage characteristic reference) reference reference LCD_BCLK [kHz] Seiko epson Corporation S1C17153 TeChniCal Manual 20-7 (Rev. 1.0)

  • Page 168: Svd Circuit Characteristics

    = 3.6V, SVDC[4:0] = 0xe (2.0V) – µA *1 This value is added to the current consumption during SLEEP/HALT/execution (with or without heavy load protection mode) when the SVD circuit is active. Seiko epson Corporation 20-8 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 169: Basic External Connection Diagram

    External parts for the OSC1A oscillator circuit Symbol name Recommended part X'tal1 32 kHz crystal resonator C-002RX (R = 50 kW (Max.), C = 7 pF) manufactured by SEIKO EPSON Other Symbol name Recommended value Capacitor for power supply 3.3 µF Gate capacitor –...

  • Page 170: Evaluation Package

    OSC1 SEG16 OSC2 SEG15 TEST SEG14 #RESET SEG13 P00/SIN0 SEG12 P01/SOUT0 SEG11 P02/SCLK0/FOUTA SEG10 N.C. SEG9 N.C. SEG8 P03/EXCL0/LFRO N.C. P04/TOUTA0/CAPA0 SEG7 P05/TOUTB0/CAPB0/#SPISS0 SEG6 P06/BZ/SDI0 SEG5 P07/#BZ/SDO0 SEG4 P10/FOUTB/SPICLK0 SEG3 P11/BZ Seiko epson Corporation S1C17153 TeChniCal Manual 22-1 (Rev. 1.0)

  • Page 171: Appendix A List Of I/O Registers

    SND Control Register Controls buzzer outputs. generator 0x5181 SND_BZFQ Buzzer Frequency Control Register Sets the buzzer frequency. (8-bit device) 0x5182 SND_BZDT Buzzer Duty Ratio Control Register Sets the buzzer signal duty ratio. Seiko epson Corporation S1C17153 TeChniCal Manual aP-a-1 (Rev. 1.0)
  • Page 172 0xffff84 IDIR Processor ID Register Indicates the processor ID. note: Addresses marked as “Reserved” or unused peripheral circuit areas not marked in the table must not be accessed by application programs. Seiko epson Corporation aP-a-2 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 173: 0X4100-0X4107, 0X506C

    Clock source select UTCLKSRC 0x0 R/W Clock source [1:0] [1:0] External clock reserved OSC1A OSC3B – reserved – – – 0 when being read. uTClKe UART clock enable 1 Enable 0 Disable Seiko epson Corporation S1C17153 TeChniCal Manual aP-a-3 (Rev. 1.0)

  • Page 174: 0X4240-0X4248

    (slave) 1 ss = L 0 ss = H SPRBF Receive data buffer full flag 1 Full 0 Not full SPTBe Transmit data buffer empty flag 1 Empty 0 Not empty Seiko epson Corporation aP-a-4 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 175: 0X5000-0X5003

    0 when being read. Control Register (8 bits) OSC3Ben OSC3B enable 1 Enable 0 Disable (ClG_CTl) OSC1en OSC1A enable 1 Enable 0 Disable – reserved – – – 0 when being read. Seiko epson Corporation S1C17153 TeChniCal Manual aP-a-5 (Rev. 1.0)
  • Page 176 LCD clock source select LCDTCLK 0x0 R/W Clock source SRC[1:0] SRC[1:0] 0x3, 0x2 reserved OSC1A OSC3B – reserved – – – 0 when being read. lCDTClKe LCD clock enable 1 Enable 0 Disable Seiko epson Corporation aP-a-6 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 177: 0X5100-0X5102

    1.98 V reserved 0xd–0x0 SVD Detection 0x5102 D7–1 – reserved – – – 0 when being read. Result Register (8 bits) SVDDT × (SVD_RSlT) SVD detection result 1 Low 0 Normal Seiko epson Corporation S1C17153 TeChniCal Manual aP-a-7 (Rev. 1.0)

  • Page 178: 0X5120

    P0 Port 0x5207 D7–0 P0iF[7:0] P0[7:0] port interrupt flag 1 Cause of 0 Cause of R/W Reset by writing 1. interrupt Flag (8 bits) interrupt interrupt not Register occurred occurred (P0_iFlG) Seiko epson Corporation aP-a-8 S1C17153 TeChniCal Manual (Rev. 1.0)
  • Page 179 0x0 R/W reserved FOUTA SCLK0 D3–2 P01MuX[1:0] P01 port function select P01MUX[1:0] Function 0x0 R/W reserved reserved SOUT0 D1–0 P00MuX[1:0] P00 port function select P00MUX[1:0] Function 0x0 R/W reserved reserved SIN0 Seiko epson Corporation S1C17153 TeChniCal Manual aP-a-9 (Rev. 1.0)

  • Page 180: 0X5324-0X532C

    PSR overflow (V) flag 1 1 (set) 0 0 (cleared) PSRZ PSR zero (Z) flag 1 1 (set) 0 0 (cleared) PSRn PSR negative (N) flag 1 1 (set) 0 0 (cleared) Seiko epson Corporation aP-a-10 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 181: 0X5068, 0X5400-0X540C

    CCA0 = LSB Data Register (T16a_CCa0) T16a 0x5408 D15–0 CCB[15:0] Compare/capture B data 0x0 to 0xffff 0x0 R/W Comparator/ (16 bits) CCB15 = MSB Capture Ch.0 B CCB0 = LSB Data Register (T16a_CCB0) Seiko epson Corporation S1C17153 TeChniCal Manual aP-a-11 (Rev. 1.0)

  • Page 182: 0X54B0

    AM/PM 1 PM 0 AM Register – reserved – – – 0 when being read. (RTC_h) D5–0 RTChOuR Hour counter 0x0 to 0x17 (binary mode) [5:0] 0x00 to 0x23 (BCD mode) Seiko epson Corporation aP-a-12 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 183: 0Xffff84

    OF i/O ReGiSTeRS 0xffff84 S1C17 Core i/O Register name address name Function Setting init. R/W Remarks Processor iD 0xffff84 D7–0 iDiR[7:0] Processor ID 0x10 0x10 Register (8 bits) 0x10: S1C17 Core (iDiR) Seiko epson Corporation S1C17153 TeChniCal Manual aP-a-13 (Rev. 1.0)

  • Page 184: Appendix B Power Saving

    Peripheral circuits that use PCLK • Interrupt controller • 8-bit timer Ch.0 • SPI Ch.0 • Power generator • P ports and port MUX (control registers, chattering filters) • MISC registers Seiko epson Corporation S1C17153 TeChniCal Manual aP-B-1 (Rev. 1.0)
  • Page 185 Started up by an RTC interrupt. 3. Startup by OSC1A peripheral circuit Started up by a clock timer or watchdog timer interrupt. 4. Startup by PCLK peripheral circuit Started up by a PCLK peripheral circuit interrupt. Seiko epson Corporation aP-B-2 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 186: Reducing Power Consumption Via Power Supply Control

    Turn off heavy load protection for normal operations. Turn on only if the display is unstable. Power supply voltage detection (SVD) circuit • Operating the SVD circuit will increase current consumption. Turn off power supply voltage detection unless it is required. Seiko epson Corporation S1C17153 TeChniCal Manual aP-B-3 (Rev. 1.0)

  • Page 187: Appendix C Mounting Precautions

    (2) If a bypass capacitor is connected between V and V , connections between the V and V pins should be as short as possible. Seiko epson Corporation S1C17153 TeChniCal Manual aP-C-1 (Rev. 1.0)
  • Page 188 (2) Electromagnetically-induced noise from a solder iron when soldering In particular, during soldering, take care to ensure that the soldering iron GND (tip potential) has the same po- tential as the IC GND. Seiko epson Corporation aP-C-2 S1C17153 TeChniCal Manual (Rev. 1.0)

  • Page 189: Appendix D Measures Against Noise

    • Execute the resending process via software after executing the receive error handler with a parity check. For details of the pin functions and the function switch control, see the “I/O Ports (P)” chapter. For the UART control and details of receive errors, see the “UART” chapter. Seiko epson Corporation S1C17153 TeChniCal Manual aP-D-1 (Rev. 1.0)

  • Page 190: Appendix E Initialization Routine

    Xld.a %r1, 0x54b0 ; ROMC register address ; Flash read wait cycle Xld.a %r0, 0x00 ; No wait ...(5) ld.b [%r1], %r0 ; [0x54b0] <= 0x00 ; ===== Main routine ========================================= Seiko epson Corporation S1C17153 TeChniCal Manual aP-e-1 (Rev. 1.0)
  • Page 191 (3) The program code is written in the “.text” section. (4) Sets the stack pointer. (5) Sets the number of ROM read wait cycles. Can be set to no wait in the S1C17153. (See the “Memory Map, Bus Control” chapter.) Seiko epson Corporation...

  • Page 192: Appendix F Mask Rom Code Development

    Appendix F Mask ROM Code Development You can use the S1C17653, which includes a Flash memory and all the S1C17153 functions, for developing mask ROM codes for the S1C17153. However, take the differences shown below into consideration and make sue that the codes do not access to the functions not implemented in the S1C17153.

  • Page 193: Revision History

    ReViSiOn hiSTORY Revision history Code no. Page Contents 412495700 New establishment...
  • Page 194 Fax: +886-2-8786-6660 ePSOn SinGaPORe PTe., lTD. 1 HarbourFront Place, #03-02 HarbourFront Tower One, Singapore 098633 Phone: +65-6586-5500 Fax: +65-6271-3182 SeiKO ePSOn CORP. KORea OFFiCe 5F, KLI 63 Bldg., 60 Yoido-dong, Youngdeungpo-Ku, Seoul 150-763, KOREA Phone: +82-2-784-6027 Fax: +82-2-767-3677 SeiKO ePSOn CORP.

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