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S1C17153
Seiko Epson S1C17153 Manuals
Manuals and User Guides for Seiko Epson S1C17153. We have
1
Seiko Epson S1C17153 manual available for free PDF download: Technical Manual
Seiko Epson S1C17153 Technical Manual (194 pages)
CMOS 16-BIT SINGlE CHIP MICROCONTROLLER
Brand:
Seiko Epson
| Category:
Microcontrollers
| Size: 3 MB
Table of Contents
Table of Contents
4
1 Overview
10
Features
10
Block Diagram
11
Pads
12
Pad Configuration Diagram
12
Pin Descriptions
14
2 Cpu
15
Features of the S1C17 Core
15
CPU Registers
16
Instruction Set
16
Reading PSR
19
Processor Information
20
3 Memory Map, Bus Control
21
Bus Cycle
21
Restrictions on Access Size
22
Restrictions on Instruction Execution Cycles
22
Internal ROM Area
22
Embedded ROM
22
ROM Read Wait Cycle Setting
22
ROMC Read Wait Control Register (ROMC_WAIT)
22
Internal RAM Area
23
Embedded RAM
23
Display RAM Area
23
Internal Peripheral Area
23
Internal Peripheral Area 1 (0X4000-)
23
Internal Peripheral Area 2 (0X5000-)
23
S1C17 Core I/O Area
24
4 Power Supply
25
Power Supply Voltage
25
Internal Power Supply Circuit
25
D1 Regulator
25
LCD Power Supply Circuit
25
Heavy Load Protection Mode
26
Control Register Details
27
LCD Booster Clock Control Register (LCD_BCLK)
27
LCD Voltage Regulator Control Register (LCD_VREG)
28
D1 Control Register (VD1_CTL)
29
5 Initial Reset
30
Initial Reset Sources
30
RESET Pin
30
P0 Port Key-Entry Reset
30
Resetting by the Watchdog Timer
30
Initial Reset Sequence
31
Initial Settings after an Initial Reset
31
6 Interrupt Controller (Itc)
32
ITC Module Overview
32
Vector Table
33
Vector Table Address Low/High Registers (MISC_TTBRL, MISC_TTBRH)
34
Control of Maskable Interrupts
34
Interrupt Control Bits in Peripheral Modules
34
ITC Interrupt Request Processing
34
Interrupt Processing by the S1C17 Core
35
Nmi
35
Software Interrupts
35
HALT and SLEEP Mode Cancellation
36
Control Register Details
36
Interrupt Level Setup Register X (Itc_Lvx)
36
7 Clock Generator (Clg)
38
CLG Module Overview
38
CLG Input/Output Pins
39
Oscillators
39
OSC3B Oscillator
39
OSC1A Oscillator
40
System Clock Switching
42
CPU Core Clock (CCLK) Control
43
Peripheral Module Clock (PCLK) Control
43
Clock External Output (FOUTA, FOUTB)
44
Control Register Details
45
Clock Source Select Register (CLG_SRC)
45
Oscillation Control Register (CLG_CTL)
46
FOUTA Control Register (CLG_FOUTA)
47
FOUTB Control Register (CLG_FOUTB)
48
Oscillation Stabilization Wait Control Register (CLG_WAIT)
48
PCLK Control Register (CLG_PCLK)
49
CCLK Control Register (CLG_CCLK)
50
8 Real-Time Clock (RTC)
52
RTC Module Overview
52
RTC Counters
52
RTC Control
54
Operating Clock Control
54
12-Hour/24-Hour Mode Selection
54
RTC Start/Stop
54
Counter Settings
54
Counter Read
55
RTC Interrupts
56
Control Register Details
56
RTC Control Register (RTC_CTL)
56
RTC Interrupt Enable Register (RTC_IEN)
57
RTC Interrupt Flag Register (RTC_IFLG)
58
RTC Minute/Second Counter Register (RTC_MS)
59
RTC Hour Counter Register (RTC_H)
60
9 I/O Ports (P)
61
P Module Overview
61
Input/Output Pin Function Selection (Port MUX)
62
Data Input/Output
62
Pull-Up Control
63
Port Input Interrupt
63
P0 Port Chattering Filter Function
64
P0 Port Key-Entry Reset
65
Control Register Details
65
Px Port Input Data Registers (Px_In)
65
Px Port Output Data Registers (Px_Out)
66
Px Port Output Enable Registers (Px_Oen)
66
Px Port Pull-Up Control Registers (Px_Pu)
66
P0 Port Interrupt Mask Register (P0_IMSK)
67
P0 Port Interrupt Edge Select Register (P0_EDGE)
67
P0 Port Interrupt Flag Register (P0_IFLG)
67
P0 Port Chattering Filter Control Register (P0_CHAT)
68
P0 Port Key-Entry Reset Configuration Register (P0_KRST)
69
Px Port Input Enable Registers (Px_Ien)
69
P0[3:0] Port Function Select Register (P00_03PMUX)
70
P0[7:4] Port Function Select Register (P04_07PMUX)
71
P1[3:0] Port Function Select Register (P10_13PMUX)
72
10 8-Bit Timer (T8)
73
T8 Module Overview
73
Count Clock
74
Reload Data Register and Underflow Cycle
74
Timer Reset
75
Timer RUN/STOP Control
75
T8 Output Signals
76
T8 Interrupts
76
Control Register Details
77
T8 Ch.X Count Clock Select Register (T8_Clkx)
77
T8 Ch.X Reload Data Register (T8_Trx)
77
T8 Ch.X Counter Data Register (T8_Tcx)
78
T8 Ch.X Control Register (T8_Ctlx)
78
T8 Ch.X Interrupt Control Register (T8_Intx)
79
16-Bit PWM Timer (T16A2)
80
T16A2 Module Overview
80
T16A2 Input/Output Pins
81
Count Clock
81
T16A2 Operating Modes
82
Comparator Mode and Capture Mode
83
Repeat Mode and One-Shot Mode
84
Normal Clock Mode and Half Clock Mode
84
Counter Control
85
Counter Reset
85
Counter RUN/STOP Control
85
Reading Counter Values
85
Counter Operation and Interrupt Timing Charts
86
Timer Output Control
86
T16A2 Interrupts
88
Control Register Details
90
T16A Clock Control Register Ch.X (T16A_Clkx)
90
T16A Counter Ch.X Control Register (T16A_Ctlx)
91
T16A Counter Ch.X Data Register (T16A_Tcx)
93
T16A Comparator/Capture Ch.X Control Register (T16A_Ccctlx)
93
T16A Comparator/Capture Ch.X a Data Register (T16A_Ccax)
95
T16A Comparator/Capture Ch.X B Data Register (T16A_Ccbx)
95
T16A Comparator/Capture Ch.X Interrupt Enable Register (T16A_Ienx)
96
T16A Comparator/Capture Ch.X Interrupt Flag Register (T16A_Iflgx)
97
12 Clock Timer (CT)
99
CT Module Overview
99
Operation Clock
99
Timer Reset
99
Timer RUN/STOP Control
100
CT Interrupts
100
Control Register Details
101
Clock Timer Control Register (CT_CTL)
101
Clock Timer Counter Register (CT_CNT)
102
Clock Timer Interrupt Mask Register (CT_IMSK)
102
Clock Timer Interrupt Flag Register (CT_IFLG)
102
13 Watchdog Timer (WDT)
104
WDT Module Overview
104
Operation Clock
104
WDT Control
104
Nmi/Reset Mode Selection
104
WDT Run/Stop Control
105
WDT Reset
105
Operations in HALT and SLEEP Modes
105
Control Register Details
105
Watchdog Timer Control Register (WDT_CTL)
105
Watchdog Timer Status Register (WDT_ST)
106
14 Uart
107
UART Module Overview
107
UART Input/Output Pins
108
Baud Rate Generator
108
Transfer Data Settings
110
Data Transfer Control
111
Receive Errors
113
UART Interrupts
114
Irda Interface
115
Control Register Details
116
UART Ch.X Status Register (Uart_Stx)
116
UART Ch.X Transmit Data Register (Uart_Txdx)
118
UART Ch.X Receive Data Register (Uart_Rxdx)
118
UART Ch.X Mode Register (Uart_Modx)
118
UART Ch.X Control Register (Uart_Ctlx)
119
UART Ch.X Expansion Register (Uart_Expx)
120
UART Ch.X Baud Rate Register (Uart_Brx)
120
UART Ch.X Fine Mode Register (Uart_Fmdx)
121
UART Ch.X Clock Control Register (Uart_Clkx)
121
15 Spi
123
SPI Module Overview
123
SPI Input/Output Pins
123
SPI Clock
124
Data Transfer Condition Settings
124
Data Transfer Control
125
SPI Interrupts
127
Control Register Details
128
SPI Ch.X Status Register (Spi_Stx)
128
SPI Ch.X Transmit Data Register (Spi_Txdx)
129
SPI Ch.X Receive Data Register (Spi_Rxdx)
129
SPI Ch.X Control Register (Spi_Ctlx)
129
16 Lcd Driver (Lcd)
132
LCD Module Overview
132
LCD Power Supply
132
LCD Clock
133
LCD Operating Clock (LCLK)
133
Frame Signal
134
Drive Duty Control
134
Drive Duty Switching
134
Drive Waveform
135
Display Memory
138
Display Control
139
Display On/Off
139
Inverted Display
139
LCD Interrupt
140
Control Register Details
140
LCD Timing Clock Select Register (LCD_TCLK)
140
LCD Display Control Register (LCD_DCTL)
141
LCD Clock Control Register (LCD_CCTL)
142
LCD Voltage Regulator Control Register (LCD_VREG)
143
LCD Interrupt Mask Register (LCD_IMSK)
143
LCD Interrupt Flag Register (LCD_IFLG)
143
17 Sound Generator (Snd)
144
SND Module Overview
144
SND Output Pins
144
SND Operating Clock
144
Buzzer Frequency and Volume Settings
145
Buzzer Frequency
145
Volume Level
145
Buzzer Mode and Output Control
146
Buzzer Mode Selection
146
Output Control in Normal Mode
146
Output Control in One-Shot Mode
146
Output Control in Envelope Mode
147
Control Register Details
148
SND Clock Control Register (SND_CLK)
148
SND Control Register (SND_CTL)
148
Buzzer Frequency Control Register (SND_BZFQ)
150
Buzzer Duty Ratio Control Register (SND_BZDT)
150
18 Supply Voltage Detection Circuit (SVD)
151
SVD Module Overview
151
Comparison Voltage Setting
151
SVD Control
152
Control Register Details
152
SVD Enable Register (SVD_EN)
152
SVD Comparison Voltage Register (SVD_CMP)
153
SVD Detection Result Register (SVD_RSLT)
154
19 Multiplier/Divider (COPRO)
155
Overview
155
Operation Mode and Output Mode
155
Multiplication
156
Division
157
Mac
158
Reading Operation Results
160
20 Electrical Characteristics
161
Absolute Maximum Ratings
161
Recommended Operating Conditions
161
Current Consumption
161
Oscillation Characteristics
163
External Clock Input Characteristics
163
Input/Output Pin Characteristics
163
SPI Characteristics
165
LCD Driver Characteristics
165
SVD Circuit Characteristics
168
21 Basic External Connection Diagram
169
22 Evaluation Package
170
Appendix A List of I/O Registers
171
0X4100-0X4107, 0X506C
173
UART (with Irda) Ch.0
173
0X4240-0X4248
174
8-Bit Timer Ch.0
174
0X4306-0X4314
174
Interrupt Controller
174
0X4320-0X4326
174
SPI Ch.0
174
0X5000-0X5003
175
Clock Timer
175
0X5040-0X5041
175
Watchdog Timer
175
0X5060-0X5081
175
Clock Generator
175
0X5100-0X5102
177
SVD Circuit
177
0X5120
178
Power Generator
178
0X506E, 0X5180-0X5182
178
Sound Generator
178
0X5200-0X52A2
178
P Port & Port MUX
178
0X5324-0X532C
180
MISC Registers
180
0X5068, 0X5400-0X540C
181
16-Bit PWM Timer Ch.0
181
0X54B0
182
ROM Controller
182
0X56C0-0X56C8
182
Real-Time Clock
182
0Xffff84
183
S1C17 Core I/O
183
Appendix B Power Saving
184
Clock Control Power Saving
184
Reducing Power Consumption Via Power Supply Control
186
Appendix C Mounting Precautions
187
Appendix D Measures against Noise
189
Appendix E Initialization Routine
190
Appendix F Mask ROM Code Development
192
Revision History
193
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