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CMOSTEK CMT2281F2 User Manual

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Summary
CMT2281F2 is a low power, high performance OOK RF receiver chip.It covers a 300 MHz - 960MHz wireless
communication band with a RISC Flash type MCU embedded in it. It belongs to the CMOSTEK
NextGenRFTM series product.The product series include short range wireless communication chips, such as
transmitter, receiver, transceiver,SoC and so on.
The part numbers covered by this document are as shown below.
Part No.
CMT22181F2
Note：The test conditions for sensitivity and Rx current are at 433.92MHz, 1kbps, 0.1% BER
Copyright © By CMOSTEK
CMT2281F2 User Guide
Table1.
Part Numbers Covered by This Document
Frequency
Modem
300 MHz -
OOK
960MHz
Rx
Sensitivity
Current
-109dBm
4.5mA
Page 1/86
AN200
AN200
Configuration
Package
Embedded
SOP16
MCU
www.cmostek.com

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  • Page 1 CMT2281F2 User Guide Summary CMT2281F2 is a low power, high performance OOK RF receiver chip.It covers a 300 MHz - 960MHz wireless communication band with a RISC Flash type MCU embedded in it. It belongs to the CMOSTEK NextGenRFTM series product.The product series include short range wireless communication chips, such as transmitter, receiver, transceiver,SoC and so on.

  • Page 2: Table Of Contents

    Bank0 SFR ........................26 4.1.2 Bank1 SFR ........................27 4.1.3 TMR0（Addr:0x01） ......................28 4.1.4 STATUS（Addr:0x03） ..................... 28 4.1.5 PORTA（Addr:0x05） ....................... 29 4.1.6 PORTC（Addr:0x07） ...................... 30 4.1.7 INTCON（Addr:0x0B）..................... 30 4.1.8 PIR1（Addr:0x0C） ......................31 4.1.9 TMR2（Addr:0x11） ......................32 4.1.10 T2CON（Addr:0x12）....................... 32 www.cmostek.com Page 2/86...
  • Page 3 Clock Switching Timing of HFINTOSC and LFINTOSC ............ 50 Clock Switching ......................... 51 5.4.1 System Clock Select Bit (SCS) ..................51 5.4.2 Oscillator Start-up Timeout Status(OSTS) Bit ..............52 Two-Speed Clock Start-up Mode ....................52 5.5.1 Two-Speed Start-up Mode Configuration ................52 www.cmostek.com Page 3/86...
  • Page 4 Interrupt Response ........................71 14.4 Context Saving During Interrupts ....................72 15 MCU Sleep Mode ............................ 73 15.1 Wake-up Mode .......................... 73 15.2 Watchdog Wake-up ........................73 16 I/O Port ..............................74 16.1 PORTA Port and TRISA Register ....................74 www.cmostek.com Page 4/86...
  • Page 5 16.3.3 PORTA4 ..........................78 16.3.4 PORTA5 ..........................79 16.3.5 PORTA6 ..........................80 16.3.6 PORTA7 ..........................81 16.3.7 PORTC<7:0> ........................82 17 Instruction Set List ..........................83 18 Document Modification Record ......................85 19 Contact Information ..........................86 www.cmostek.com Page 5/86...

  • Page 6: Chip Architecture Introduction

    1 Chip Architecture Introduction 1.1 Overall Operation Principle CMT2281F2 is a digital analog integrated receiver MCU. It uses the crystal oscillator to provide the reference frequency and digital clock for PLL, and supports the OOK demodulation output from 1Kbps to 40Kbps, and supports the Duty-Cycle mode based on MCU program control.

  • Page 7: Io Pin Description

    VDDL RFIN PC4/SDIO/RFDATA DVDD AVDD/PC0 PA6/OSC2/CLKO PA5/MCLRB PA7/OSC1/CLKI PA1/C1IN-/ICSPDAT PA0/C1IN+/ICSPCLK PA2/T0CKI/INT/C1OUT Figure 1-2. CMT2281F2 Pin Top View Table 1-1.CMT2281F2 SOP16 Pin Description Pin No. Name Type Function Description VDDL Digital Reference Voltage, needs to connect the external filter capacitor. RFIN...
  • Page 8 2. IOC is IO change wake-up, that is,port level edge jumping wake-up function; 3. PC3/CSB and PC2/SCLK are the internal control pins of the chip and have no the package terminals.  When CSB=1, PC4/SDIO/RFDATA is used for RFDATA.  When CSB=0, PC4/SDIO/RFDATA is used for SDIO. www.cmostek.com Page 8/86...

  • Page 9: Rf Configuration And Control Mechanism

    AN200 2 RF Configuration and Control Mechanism 2.1 Working Mode and Status There are two working modes for the OOK receiving function of CMT2281F2.  Simple Work mode: Default entry mode on power-up  Advanced Configuration mode: Configure the register and control the operation status through the SPI Bus 2.2 Simple Work Mode...

  • Page 10: Auto Cycle Reset Function

    2.2.3 Auto Cycle Reset Function Auto Cycle Reset, as the name implies, periodically and automatically resets the CMT2281F2 RF part to the POR status, and then re-TUNEs and enters the Rx status.Its role is to prevent the chip from abnormality in various complex application environments due to unpredictable external factors, including configuration anomalies, frequency locking anomalies, voltage anomalies, and so on.When an abnormal operation cycle...

  • Page 11: Low Power Processing

    Select the appropriate bandwidth to improve the reception effect.  Support more rate selection and support high rate communication applications. 2.3.1 Work Status The advanced configuration mode can control the status switching of the RF part through the SPI, as shown in the following figure: www.cmostek.com Page 11/86...

  • Page 12: Initialization Of Configuration Parameters And Configuration Process

    Reset STBY Figure 2-3. CMT2281F2 RF Part Manual Work Mode Status Switching Diagram 2.3.2 Initialization of configuration parameters and configuration process In the advanced configuration mode, the RF part needs the initial operation of the MCU by configuring the registers through the SPI (INI in Figure 2-3), while the configuration parameters need to be exported for the equivalent use by CMT2210LH on RFPDK.The specific way is: users fill the needed operation frequency and...
  • Page 13 Figure 2-4. Configuration Interface of CMT2210LH RFPDK The user clicks on Export, and RFPDK will export an”.exp” file, as shown below: ;------------------------------------------------------------------------- ; CMT2210LH Configuration File ; Generated by CMOSTEK RFPDK 1.46 Beta ; 2017.11.06 16:04 ;------------------------------------------------------------------------- ; Mode = Advanced ;...
  • Page 14 ; The following is the CRC result for ; the above EEPROM contents ;------------------------------------------------------------------------- 0x5618 ;------------------------------------------------------------------------- ; The following are for CMOSTEK ; use, customers can ignore them ;------------------------------------------------------------------------- 0x0000 0x0010 In the files exported above, the displayed content that RF needs to be configured (the red font) can be completed by writing the register.Therefore, the user needs to convert the 16-bit data format into the 8-bit...
  • Page 15 AN200 Table 2-1. CMT2281F2 Parameter List Register 8-bit Register 16-bitWord Address Content 0x00 0x5C 0x2E5C 0x01 0x2E 0x02 0xD0 0x10D0 0x03 0x10 0x04 0x00 0x0100 0x05 0x01 0x06 0xDD 0xA0DD 0x07 0xA0 0x08 0xA1 0x0BA1 0x09 0x0B 0x0A 0x50 0xE150...

  • Page 16: Control Register

    2.3.3 Control Register The user needs to know and master the control register about the RF status. The following is the overview of this part of the registers: Table 2-2. RF Part Registers Overview Table inside CMT2281F2 Address Name Bit 7...
  • Page 17 000：IDLE, the transient status of power-up, please ignore it. CHIP_MODE_STA<3:0> 010：STBY, standby status 100：RX, receiving status CUS_MODE_CTL Others: Transition status or invalid status, (0x22) please ignore it. Status switching commands: 0010：go_stby CHIP_MODE_SWT<3:0> 1000：go_rx Others: not allowed to send. www.cmostek.com Page 17/86...
  • Page 18 2.3.10 in (0x24) detail. Table 2-8. CUS_SOFTRST Register Function Description Register Name Bit Name Function Description The soft reset command of RF part, send CUS_SOFTRST SOFTRST 0xFF, and please see the chapter 2.3.5 in (0x3F) detail. www.cmostek.com Page 18/86...

  • Page 19: Detailed Description Of The Operation Status

    <= N ms <= about 2.5 ms <= 1 ms Figure 2-5. CMT2281F2 RF Part Power-up Flow Chart  INI Process INI is not a status, but it refers to the initialization process mentioned in the previous article, which is switched from the power-up default work mode to the manual work mode.This process only needs to be done once on...

  • Page 20: Soft Reset（Softrst

    Table 2-9 and Table 2-10, and are handled according to the "Closing process" and "Opening process" below. Table 2-9. CMT2281F2RF Status and Module Opening Table Switching Status Binary code Opening module command IDLE soft_rst 5V-PAD, POR STBY go_stby 5V-PAD, POR, XTAL, DLDO, LFOSC www.cmostek.com Page 20/86...
  • Page 21 Set PD_DLDO to 0, wait for 200us; Set LV_RSTN to 1; Set PD_XO to 0, wait for 5ms; Set PD_LFOSC to 0; Set LV_RSTN_SEL to 0; Set PD_XO_DLDO_SEL to 0; Set PD_LFOSC_SEL to 0; www.cmostek.com Page 21/86...

  • Page 22: Rf Control Interface Timing

    CMT2210LH, so the equivalent configuration parameters can be set by CMT2210LH on RFPDK, which is only suitable for the advanced www.cmostek.com Page 22/86...

  • Page 23: Rssi Detection And Reading

    SNR is less than 10 dB, then the threshold is set to 30 Note: The mute function setting can be done on the RFPDK and is only applicable to the Average demodulation mode; the Middle demodulation mode does not support it. www.cmostek.com Page 23/86...

  • Page 24: Battery Voltage Detection

    Because the voltage measurement is not real time, it is only once when it enters the Rx status. So when the user needs to measure, it is recommended to switch to STBY and then switch back to the Rx, triggering the voltage measurement. www.cmostek.com Page 24/86...

  • Page 25: Program Memory

    The user and factory configuration information bank is 0x2000~0x203F. 0x000 Code 0x7FF 0x2000 UCFG0 0x2001 UCFG1 0x2002 UCFG2 Reserve (not used) 0x2010 FCFG0 0x2011 FCFG1 0x2012 FCFG2 0x2020 INFOx 0x1FFF 0x2000 0x203F 0x203F Figure 3-1. Program Space Address Mapping www.cmostek.com Page 25/86...

  • Page 26: Special Function Register(Sfr)

    - - - - 1 1 1 1 - - - - - - - - - - - - - - - - Bank0’s SRAM, which is general RAM of 96Bytes. 20-7F x x x x x x x x www.cmostek.com Page 26/86...

  • Page 27: Bank1 Sfr

    C0-EF - - - - - - - - F0-FF ccess Bank0’s 0x70～0x7F. x x x x x x x x SRAM, A Note: INDF is not a physical register. www.cmostek.com Page 27/86...

  • Page 28: Tmr0（Addr:0X01

    4 low-order bit of the result occurred Carry/ bit(ADDWF、ADDLW、SUBLW、SUBWF instructions) 1 = A carry/ from the Most Significant bit of the result occurred 0 = No carry/ from the Most Significant bit of the result occurred www.cmostek.com Page 28/86...

  • Page 29: Porta（Addr:0X05

    PORTA Reset Type Table 4-8. PORTA Bit Function Description Name Function PORTA7 data PORTA6 data PORTA5 only has the input function.There is no corresponding output data register. PORTA4 data PORTA3 data PORTA2 data PORTA1 data PORTA0 data www.cmostek.com Page 29/86...

  • Page 30: Portc（Addr:0X07

    1 = Enable all unmasked interrupts 0 = Disable all interrupts Peripheral Interrupt Enable bit PEIE 1 = Enable all unmasked peripheral interrupts 0 = Disable all peripheral interrupts Timer0 Overflow Interrupt Enable bit T0IE 1 = Enable 0 = Disable www.cmostek.com Page 30/86...

  • Page 31: Pir1（Addr:0X0C

    Reserved-bit, can not be written as “1” Comparator2 Interrupt Flag bit C2IF 1 = Comparator2 output has changed 0 = Comparator2 output has not changed Comparator1 Interrupt Flag bit C1IF 1 = Comparator1 output has changed 0 = Comparator1 output has not changed www.cmostek.com Page 31/86...

  • Page 32: Tmr2（Addr:0X11

    0011 = 1:4 postscale 0100 = 1:5 postscale TOUTPS<3:0> 0101 = 1:6 postscale 0110 = 1:7 postscale 0111 = 1:8 postscale 1000 = 1:9 postscale 1001 = 1:10 postscale 1010 = 1:11 postscale 1011 = 1:12 postscale www.cmostek.com Page 32/86...

  • Page 33: Wdtcon（Addr:0X18

    0110 = 1:2048 0111 = 1:4096 1000 = 1:8192 1001 = 1:16384 1010 = 1:32768 1011 = 1:65536 11xx = 1:65536 Software Enable or Disable the watchdog timer SWDTEN 1 =WDT is turned on 0 =WDT is turned off www.cmostek.com Page 33/86...

  • Page 34: Cmcon0（Addr:0X19

    000 = The comparator is turned off , and the CxIN pin is the analog IO pin CM<2:0> 001 = Three inputs multiplexed to two comparators 010 = Four inputs multiplexed to two comparators 011 = Two common reference comparators www.cmostek.com Page 34/86...

  • Page 35: Pr0（Addr:0X1A

    LVR is disabled regardless of SLVREN value. Reserved-bit, can not be written as“1” Measurement average mode of fast clock measuring slow clock cycle CKMAVG 1 = Open the average mode(Automatically measure and accumulate four times) 0 = Close the average mode www.cmostek.com Page 35/86...

  • Page 36: Soscpr（Addr:0X1C/0X1D

    /PAPU INTEDG T0CS T0SE PS<2:0> Reset Type Table 4-30. OPTION Bit Function Description Name Function PORTA Pull-up Enable bit /PAPU 1 = PORTA pull-ups are disabled 0 = PORTA pull-ups are enabled by individual port latch values www.cmostek.com Page 36/86...

  • Page 37: Trisa（Addr:0X85

    Function PORTA<7:6> Port Direction Control bits TRISA<7:6> 1 = Input 0 = Output PORTA5 Port Direction Control bit TRISA<5> Only as input, fixed to 1 PORTA<4:0> Port Direction Control bits TRISA<4:0> 1 = Input 0 = Output www.cmostek.com Page 37/86...
  • Page 38 AN200 www.cmostek.com Page 38/86...

  • Page 39: Trisc（Addr:0X87

    0 = Disable the comparator2 interrupt Comparator1Interrupt Enable bit C1IE 1 = Enable the comparator1 interrupt 0 = Disable the comparator1 interrupt Oscillator Fail Interrupt Enable bit OSFIE 1 = Enable the oscillator fail interrupt 0 = Disable the oscillator fail interrupt www.cmostek.com Page 39/86...

  • Page 40: Pcon（Addr:0X8E

    Internal Low Frequency Oscillation Mode: LFMOD 1 = 256K oscillation frequency mode 0 = 32K oscillation frequency mode Internal Oscillator Frequency Select bits 111 = 16MHz 110 = 8MHz IRCF<2:0> 101 = 4MHz（default） 100 = 2MHz 011 = 1MHz www.cmostek.com Page 40/86...

  • Page 41: Pr2（Addr:0X92

    Timer2 period (comparison) register (See the Timer2 description chapter in details.) 4.1.23 WPUA（Addr:0x95） Table 4-43. WPUA Register Name Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 WPUA WPUA7 WPUA6 WPUA5 WPUA4 WPUA3 WPUA2 WPUA1 WPUA0 Reset Type www.cmostek.com Page 41/86...

  • Page 42: Ioca（Addr:0X96

    Table 4-48. VRCON Bit Function Description Name Function CVref Enable bit VREN 1 = CVref circuit powered on 0 = CVref circuit powered down, no I drain CVref Range Select bit 1 = Low level range 0 = High level range www.cmostek.com Page 42/86...

  • Page 43: Eedat（Addr:0X9A

    Other values=Inhibit write to the data EEPROM EEPROM Write Error Flag bit 1 = A write operation is prematurely terminated (any /MCLR Reset, any WDT Reset during WRERR EEPROM programming period) 0 = The write operation completed during EEPROM programming period. www.cmostek.com Page 43/86...

  • Page 44: Eecon2（Addr:0X9D

    The bit can only be rewritten from 1 to 0, but it can not be rewritten from 0 to 1.The only way to rewrite from 0 to 1 is to erase the register including USER_OPT, and the CPB becomes 1 after power-up again. www.cmostek.com Page 44/86...
  • Page 45 1 = Read the value of the PAD returned from the data port. 0 = Read the value of the Latch returned from the data port. Low Voltage Reset Select bit LVREN<1:0> 00 = Enable the Low Voltage Reset. Others= Disable the Low Voltage Reset. www.cmostek.com Page 45/86...

  • Page 46: Pcl And Pclath

    Executing any instruction with the PCL register as the destination simultaneously causes the Program Counter PC<10:8> bits to be replaced by the content of the PCLATH register.This allows the entire contents of the program counter to be changed by writing the desired upper 3-bit to the PCLATH register. www.cmostek.com Page 46/86...

  • Page 47: Indf And Fsr Register

    0~255.Any instruction that uses the INDF register is actually access to the unit that the file selection register FSR points to.Reading the INDF indirectly will return 0. Writing the INDF indirectly will cause the control operation. (It may affect the status flag bit.) www.cmostek.com Page 47/86...

  • Page 48: Mcu System Clock Source

    The prescaler ratio of the system clock source can be controlled by the IRCF<2:0> bit in the OPTION register. Note: The watchdog, the system clock source (IRCF=000) and the PWRT use the output universally after 8 frequency division, which is 32KHz, regardless of the value of the LFMOD. www.cmostek.com Page 48/86...

  • Page 49: Clock Source Mode

    LP mode is the lowest in the two modes. The design of the mode is only suited to drive the 32.768KHz tuning-fork type crystal oscillator (clock crystal oscillator). The XT oscillator mode selects the high gain setting of the internal inverter-amplifier. www.cmostek.com Page 49/86...

  • Page 50: Internal Clock Mode

    If the new clock is closed, start a clock start-up delay. The clock switching circuit waits for the arrival of the falling edge of the current clock. Hold CLKOUT to low, the clock switching circuit waits for the arrival of the falling edge oftwo new www.cmostek.com Page 50/86...

  • Page 51: Clock Switching

    The system clock selection (SCS) bit of the OSCCON register is used to select the CPU or the peripheral system clock source.  When the System Clock Select bit (SCS) of the OSCCON register is 0, the system clock source is determined by configuration of the FOSC<2:0> bit in the Configuration Word register (UCFG0). www.cmostek.com Page 51/86...

  • Page 52: Oscillator Start-Up Timeout Status(Osts) Bit

    Configure the IESObit in the Configuration Word register (UCFG1) as 1, Internal/External Switch Over bit. (Enable the Two-Speed Start-up Mode.)  Configure the SCS bit of the OSCCON register as 0.  Configure the F <2:0> in the Configuration Word register (CONFIG) as the LP or XT mode. www.cmostek.com Page 52/86...

  • Page 53: Two-Speed Start-Up Sequence

    FSCM can be enabled by setting the FCMEN bit in the Configuration Word register（UCFG1）to 1. FSCM can be used for all external oscillator modes (LP, XT and EC). External Clock （LP/XT/EC） Interrrupt LFINTOSC Prescaler ～32KHz Sample Clock Generator Figure 5-4. FSCM Schematic Block Diagram www.cmostek.com Page 53/86...

  • Page 54: Fail-Safe Detection

    (i.e., after exiting Reset or Sleep).After an appropriate amount of time, the user should check the OSTS bit of the OSCCON register to verify whether the oscillator has successfully started and whether the system clock has been switched successfully. www.cmostek.com Page 54/86...

  • Page 55: Reset Timing

    AN200 6 Reset Timing CMT2281F2 has several different resets: Power-on Reset(POR) WDT Reset during normal operation WDTWake-up during Sleep /MCLR Reset during normal operation /MCLR Reset during Sleep Brown-out Reset(BOR/LVR) Error instruction Reset (Disable) Some registers are not affectedin any Reset condition.The status of these registers is unknown on POR, and is not affected by the Reset event.

  • Page 56: Power-On Reset (Por)

    VDD will rise to a sufficiently high voltage to make the system work properly.PWRT can also be enabled www.cmostek.com Page 56/86...

  • Page 57: Brown-Out Reset (Bor（Lvr）)

    Power-on Reset, and the software must set it to 1 and check if it is 0. Bit1 is the /POR bit, which is 0 on Power-on Reset, and the software must set it to 1. www.cmostek.com Page 57/86...
  • Page 58 MCLRB SYS_RSTN Figure 6-3. Power on Reset with MCLRB POR_RSTN 4 ms delay BOOT_EN PWRTE BOOT_END PWRT_OV PWRT,64 ms MCLRB SYS_RSTN Figure 6-4. Power on Reset without MCLRB ≈ 8 ms Internal reset Figure 6-5. BOR Reset www.cmostek.com Page 58/86...
  • Page 59 Low Voltage Reset Oscillator Sleep Wake-up configuration /PWRTEB=0 /PWRTEB=1 /PWRTEB=0 /PWRTEB=1 INTOSC TPWRT TPWRT Table 6-2. STATUS/PCON Bit and Significance（U-No change，X-Unknown） /POR /BOR Condition WDT Reset WDT Wake-up /MCLR Reset during normal operation /MCLR Reset during Sleep www.cmostek.com Page 59/86...

  • Page 60: Boot

    After POR or BOR, inserting a status, the unit of EEPROM is mapped into a configuration register.The address of EEPROM starts from 2000H. The system reset is released until the end of the BOOT, as shown in Figure 6-3 and figure 6-4.The process needs about 17us. www.cmostek.com Page 60/86...

  • Page 61: Watchdog Timer

    Enter the SLEEP, exit the SLEEP Note: If the internal slow clock switches from 32K to 256K mode (or vice versa from 256K to 32K mode), it doesn't affect the watchdog timing, because WDT is fixed touse the 32K clock source. www.cmostek.com Page 61/86...

  • Page 62: Timer0

    In this mode, the timer0 adds 1 (without prescaler) in each instruction cycle.The software can clear the T0CS bit of the OPTION register to enter the timer mode.When the software writes to TMR0, the timer does not increase progressively in the following 2 cycles. www.cmostek.com Page 62/86...

  • Page 63: Timer0 Counter Mode

    OPTION_REG, PSA ；Select WDT CLRWDT ；Mask prescaler bits LDWI b’11111000’ ANDWR OPTION_REG, W ；Set WDT prescaler to 1:32 IORWI b’00000101’ LDWI OPTION_REG When the prescaler assignment is switched from WDT to TMR0, please execute the following instruction sequence. www.cmostek.com Page 63/86...

  • Page 64: Timer0 Interrupt

    In the counter mode, the synchronization between T0CKI pin input and Timer0 register is accomplished by sampling the output on the Q1 and Q2 cycles of the internal clock phase, so the high level time and low level time of the external clock source cycle must meet the relevant timing requirement. www.cmostek.com Page 64/86...

  • Page 65: Timer2

    Timer2 postscale rate increases progressively. The matching output of comparing Timer2andPR2 is sent to the Timer2 postscaler.The option range of the postscaler is from 1:1 to 1:16.The output of the Timer2 postscaler is used to set the interrupt flag bit TMR2IF www.cmostek.com Page 65/86...
  • Page 66 The Timer2 postscaler is controlled by the TOUTPS bit of the T2CON register. The prescaler counter and postscaler counter will be cleared when the following register is written:  Write TMR2  Write T2CON  Any Reset action Writing T2CON does not clear the TMR2 register. www.cmostek.com Page 66/86...

  • Page 67: Comparator

    When the word "D" is marked on the port, the user should set the corresponding TRIS bit to 0 to open the digital output driver circuit. In addition, the comparator configuration switching should mask the comparator interrupt to avoid unnecessary mistrigger events. www.cmostek.com Page 67/86...

  • Page 68: Data Eeprom

    EEDAT register.This data can therefore be read by the next instruction.EEDAT will hold this value until the user reads or writes data to the unit next time (during the write operation). BANKSEL EEADR LDWI dest_addr EEADR EECON1, RD EEDAT, W www.cmostek.com Page 68/86...

  • Page 69: Clock Measurement

    When the interrupt flag is checked to be 1, the read SOSCPR is the final result. CKMAVG BUS<1> CKCNTI MSCKCON WR CKMEAS EN T2 SYSCLK MEAS DONE SYSCLK TMR2 16-bit SOSCPR<11:0> To INT Figure 13-1. Slow Clock Measurement Mode Block Diagram www.cmostek.com Page 69/86...

  • Page 70: Interrupt Mode

    AN200 14 Interrupt Mode CMT2281F2 has the following interrupt sources:  External Interrupt PA2/INT  Timer0 Overflow Interrupt  PORTA Change Interrupt  Timer2 Match Interrupt  EEPROM Data Write Interrupt  Fail-Safe Clock Monitor Interrupt  Comparator Interrupt The Interrupt Control Register (INTCON) and the Peripheral Interrupt Request Register (PIR1) record the interrupt flag bit.

  • Page 71: Porta Level Change Interrupt

    The external interrupt includes the interrupt from the INT pin or the PORTA change interrupt, and the interrupt delay is usually 1 to 2 instruction cycles. It depends on the actual situation of the interrupt. INT（PA2） INTF 中断矢量 PC-1 PC+1 PC+2 0x004 0x005 Figure 14-1. Interrupt Response Timing Diagram www.cmostek.com Page 71/86...

  • Page 72: Context Saving During Interrupts

    W, STATUS register, and so on.These must be implemented in software.The temporary registers W_TEMP and STATUS_TEMP should be placed in the last 16bytes of the GPR. The 16bytes of GPR crosses two pages, so users can save a little bit of code space. www.cmostek.com Page 72/86...

  • Page 73: Mcu Sleep Mode

    Clearing watchdog (CLRWDT) and SLEEP instruction will clear the watchdog counter. When enabling the watchdog, the watchdog overflowing event can be used as a wake-up source when MCU is in Sleep, while it can be used as a reset source when MCU works normally. www.cmostek.com Page 73/86...

  • Page 74: O Port

    IOCAx register can enable or turn off the interrupts of these ports. The interrupt-on-change is invalid on Power-on Reset. When enabling the interrupt-on-change function, the current port level value is compared to the old value of www.cmostek.com Page 74/86...

  • Page 75: Port Description

    The following figure describes the internal circuit architecture of the port, and PA<2:0> can be configured as the following functional port:  GPIO  Debug serial clock (PA0)  Debug serial data (PA1)  External interrupt input (PA2)  Timer0 external clock source (PA2) www.cmostek.com Page 75/86...
  • Page 76 AN200 Data /RAPU WPUA WPUA PORTA TRISA TRISA PORTA IOCA PORTA IOCA Interrupt On Change T0CKI （PA2 Only） Figure 16-1.PA<2:0> Architecture Block Diagram www.cmostek.com Page 76/86...

  • Page 77: Porta3

    /RAPU WPUA WPUA PORTA ATEST1 EN TRISA TRISA PORTA IOCA PORTA IOCA Interrupt On Change Figure 16-2. PA3 Architecture Block Diagram Note: ATEST1 is used for internal testing, not open to users, and users can ignore it. www.cmostek.com Page 77/86...

  • Page 78: Porta4

    IR MODE ATEST0 EN TRISA TRISA PORTA IOCA PORTA IOCA Interrupt On Change Figure 16-3. PA4 Architecture Block Diagram Note: Both ATEST0 and IR are used for internal testing, not open to users, and users can ignore them. www.cmostek.com Page 78/86...

  • Page 79: Porta5

    The following figure describes the internal circuit architecture of the port, and PA5 can be configured as the following functional port:  Digital Input  External Reset MCLRE Weak MCLRE Reset MCLRE Data TRISA PORTA IOCA PORTA IOCA Interrupt On Change Figure 16-4. PA5 Architecture Block Diagram www.cmostek.com Page 79/86...

  • Page 80: Porta6

    Crystal oscillator and resonator connection  Clock output Data /RAPU WPUA 振荡器 OSC1 电路 FOSC/ WPUA CLKOUT PORTA Enable CLKOUT CLKOUT Enable Enable TRISA INTOSC/EC TRISA PORTA IOCA PORTA IOCA Interrupt On Change Figure 16-5. PA6 Architecture Block Diagram www.cmostek.com Page 80/86...

  • Page 81: Porta7

    Crystal oscillator and resonator connection  Clock input INTOSC or INTOSCIO Data /RAPU WPUA 振荡器 OSC2 电路 WPUA PORTA TRISA INTOSC or INTOSCIO TRISA PORTA IOCA PORTA IOCA Interrupt On Change Figure 16-6. PA7 Architecture Block Diagram www.cmostek.com Page 81/86...

  • Page 82: Portc<7:0

    Comparator Output (onlyPC4, but not available, because it is used to control the RF part.) (Only PC4) C2OUT Enable C2OU Data PORTC Analog Input mode TRISC TRISC To Comparator PORTC (Only PC0 & PC1) Figure 16-7. PORTC<7:0> Architecture Block Diagram www.cmostek.com Page 82/86...

  • Page 83: Instruction Set List

    AN200 17 Instruction Set List CMT2281F2 uses the reduced instruction set architecture with a total of 37 instructions, and the followings are the description of the instructions. Table 17-1. Instruction Set Table Instruction Function Operation Status Period R, b Bit clear 0->...
  • Page 84 C, HC, Z SUBWI Subtract W from imm I-W-> W C, HC, Z Note: The TMODE register of the chip refers to the OPTION, that is, the operation of the STTMD instruction is to save the W to OPTION. www.cmostek.com Page 84/86...

  • Page 85: Document Modification Record

    AN200 Document Modification Record Table 18-1.Document Modification Record Sheet Version Chapter Modification descriptions Date Initial release 2018-05-26 Update the function description of SLVREN bit. 4.1.14, 4.1.30 2018-12-19 Change LVDEN to LVREN. www.cmostek.com Page 85/86...

  • Page 86: Contact Information

    The material contained herein is the exclusive property of CMOSTEK and shall not be distributed, reproduced, or disclosed in whole or in part without prior written permission of CMOSTEK. CMOSTEK products are not authorized for use as critical components in life support devices or systems without express written approval of CMOSTEK.

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