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Table 2. ELECTRICAL SPECIFICATIONS
Description
SIGNAL DETECTION UNIT
Preamplifier gain
Equivalent IRN
Input impedance
Low Pass Filter Bandwidth
ADC input signal range
ADC resolution
ADC sampling frequency
DIGITAL
Voltage level for high input
Voltage level for low input
Voltage level for high output
Voltage level for low output
Oscillator frequency trim-
ming precision
Oscillator frequency stabili-
ty over temperature
Recommended working
frequency
Oscillator period jitter
PLL lock time
PLL tracking range
LOW DELAY PATH
Group Delay
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
5. Recommended VDDC values depend on the system clock (SYS_CLK) frequency. Table 3 gives the recommended VDDC values for different
system clocks.
6. The minimum VDDM value required for proper system functioning is 0.90 V
7. The audio performance might be slightly impacted when the RSL10 radio is turned on. Degradation depends on the duty cycle of the
communication, on the external components.
EZAIRO 7160 SL HYBRID
Symbol
Conditions
SDU
3 dB steps
PAG
SDU
Non−weighted, 30 dB gain,
IRN
100 Hz − 10 kHz
SDU
R
SDU
LPF
SDU
Referred to VREG
RANGE
SDU
RES
SDU
At slow_clock = 1.28 MHz
SF
V
IH
V
IL
V
2 mA source current
OH
V
2 mA sink current
OL
SYS_CLK
SYS_CLK
Over temperature range of
0 to 50°C
SYS_CLK
For recommended VDDC
and VDDM
RMS at System clock:
1.28 MHz, before
multiplication
For an input phase error
<2%, input reference clock
of 128 kHz, output clock of
2.56 MHz
Using the low delay path of
the Filter Engine
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Min
Typ
0
−
−
−
370
500
−
50
−1
−
12
1
−
VDDO
−
*0.8
−
−
VDDO
−
*0.8
−
−
−1
−
−1.5
−
1.28
−
−
−
−
−
−2
−
−
44
6
Max
Units
Screened
36
dB
n
20
mVrms
n
725
kOhm
n
−
kHz
+1
V
−
bits
64
kHz
−
V
n
VDDO*0.2
V
n
V
n
VDDO*0.2
V
n
+1
%
n
+1.5
%
15.36
MHz
400
ps
10
ms
n
2
%
−
ms
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