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•
Programmable Flexibility: The open−programmable
DSP−based system can be customized to the specific
signal processing needs of manufacturers. Algorithms
and features can be modified or completely new
concepts implemented without having to modify the
chip.
•
Fully Integrated Hybrid: Includes the Ezairo 7100
SoC, RSL10 radio SoC, 2 Mb of EEPROM memory,
and the necessary passive components to directly
interface with the transducers required in a hearing aid.
•
Fitting Support: Support for Microcard, HI−PRO 2,
HI−PRO USB, QuickCom, and NOAHlinkt, including
NOAHlink's audio streaming feature.
•
These devices are Pb−Free, Halogen Free/BFR Free
and are RoHS Compliant
Ezairo 7100 DSP Main Features:
•
Quad−core Architecture: Includes a CFX DSP, a
HEAR Configurable Accelerator, an Arm Cortex−M3
Processor Subsystem and a programmable Filter
Engine. The system also includes an efficient
input/output controller (IOC), system memories, input
and output stages along with a full complement of
peripherals and interfaces.
•
CFX DSP: A highly cycle−efficient, programmable
core that uses a 24−bit fixed−point, dual−MAC,
dual−Harvard architecture.
•
HEAR Configurable Accelerator: An optimized
signal processing engine designed to perform common
signal processing operations and complex standard
filterbanks.
•
Arm Cortex−M3 Processor Subsystem: A complete
subsystem that supports efficient data transfer to and
from the wireless transceiver or multiple transceivers.
•
Programmable Filter Engine: A filtering system that
allows applying a various range of pre− or post−
processing filtering, such as IIR, FIR and biquad filters.
•
Configurable System Clock Speeds: 1.28 MHz,
1.92 MHz, 2.56 MHz, 3.84 MHz, 5.12 MHz, 6.4 MHz,
7.68 MHz, 8.96 MHz, 9.60 MHz, 10.24 MHz (default
clock calibration), 12.80 MHz and 15.36 MHz to
optimize the computing performance versus power
consumption ratio. The calibration entries for these 12
EZAIRO 7160 SL HYBRID
Key Features
clock speeds are stored in the manufacturing area of the
EEPROM.
•
Ultra−high Fidelity: 85 dB system dynamic range with
up to 110 dB input signal dynamic range,
exceptionally−low system noise and low group delay.
•
Ultra−low Power Consumption: <0.7 mA @
10.24 MHz system clock (executing a tight MAC−loop
in the CFX DSP core plus a typical hearing aid
filterbank on the HEAR Configurable Accelerator).
•
Data Security: Sensitive program data can be
encrypted for storage in EEPROM to prevent
unauthorized parties from gaining access to proprietary
algorithm intellectual property.
•
High Speed Communication Interface: Fast
2
I
C−based interface for quick download, debugging and
general communication.
•
Highly Configurable Interfaces: Two PCM interfaces,
two I
interface as well as multiple GPIOs can be used to
stream configuration, control or signal data into and out
of the Ezairo 7160 SL hybrid.
RSL10 Main Features:
•
Arm Cortex−M3 Processor: A 32−bit core for
real−time applications, specifically developed to enable
high−performance low−cost platforms for a broad range
of low−power applications.
•
LPDSP32: A 32−bit Dual Harvard DSP core that
efficiently supports audio codecs required for wireless
audio communication. Various codecs are available to
customers through libraries that are included in
RSL10's development tools.
•
Radio Frequency Front−End: Based on a 2.4 GHz RF
transceiver, the RFFE implements the physical layer of
the Bluetooth low energy technology standard and other
proprietary or custom protocols.
•
Protocol Baseband Hardware: Bluetooth 5 certified
and includes support for a 2 Mbps RF link and custom
protocol options. The RSL10 baseband stack is
supplemented by support structures that enable
implementation of ON Semiconductor and customer
designed custom protocols.
www.onsemi.com
2
2
C interfaces, two SPI interfaces, a UART
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