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•
LSAD input
•
GPIOs data for the CFX
•
Arm Cortex−M3 processor PCM interface
•
Arm Cortex−M3 processor SPI interface
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Arm Cortex−M3 processor I
•
Arm Cortex−M3 processor GPIOs
More details on the Ezairo 7160 SL external interfaces can
be found in the Ezairo 7100 Hardware Reference Manual.
The 12 DIOs are split into two power domains as follow:
•
DIO4, DIO5, DIO6, DIO7, DIO8 and DIO9 are at the
VDBL voltage.
•
DIO20, DIO21. DIO22, DIO23, DIO24 and DIO29 are
at the VBAT voltage.
5 DIOs of the RSL10 are routed out of the Ezairo 7160 SL
hybrid:
•
RFIO0, shared with DIO11 of the Ezairo 7100
•
RFIO1, shared with DIO12 of the Ezairo 7100
•
RFIO2, shared with DIO13 of the Ezairo 7100
•
RFIO3, shared with DIO14 of the Ezairo 7100
•
RFIO12
The debug port pads for the Ezairo 7100 SDA and SCL are
at the VBAT voltage.
Pre Suite Firmware Bundle
The default firmware image loaded in the EEPROM of
Ezairo 7160 SL provides a real−time framework and suite of
advanced sound processing algorithms ideal for full
featured, wireless hearing aids (available under NDA). For
additional details about the Pre Suite firmware bundle for
Ezairo 7160 SL refer to ANDXXXX/D.
The default application leaves the debug port of Ezairo
7160 SL in Restricted Mode. It is possible to erase the
default application and replace it with your own firmware
image provided you first use the Jump ROM functions
"Wipe" and "Unlock" to place the device in Unrestricted
Mode. Refer to the Communication Protocols Manual for
Ezairo 7100 for more information.
EZAIRO 7160 SL HYBRID
2
C interface
Default Algorithms on Ezairo 7160 SL
www.onsemi.com
Debug Ports
2
The CFX's I
C interfaces share the same I
the Ezairo 7100 chip with two other I
2
CFX Debug Port I
C
The CFX debug port I
for the Ezairo 7100 system that is always enabled regardless
of the configuration of the general−purpose I
The debug port implements the debug port protocol
command set and is tightly coupled with the CFX DSP and
the memory components attached to the CFX. The default
address is 0x60.
Arm Cortex−M3 Processor Debug Port I
The Arm Cortex−M3 debug port I
hardware debugger for the Ezairo 7100 system that is always
enabled regardless of the configuration of the general−
2
purpose I
C interface. The debug port implements an Arm
Cortex−M3 processor debug port protocol command set that
is tightly coupled with the Arm Cortex−M3 processor and
the memory components attached to this core. The default
address is 0x40.
The Arm Cortex−M3 processor of the RSL10 can be
debugged through the SWJ−DP which can be configured to
either serial wire or JTAG debug port communications. By
default, the SWJ−DP is accessed using the JTAG dedicated
pads (JTCK, JTMS).
Frequency Response Graph
Conditions
SYS_CLK = 10.24 MHz
Firmware: Simple FIFO copy application
Gain normalized to 0 dB at 1 kHz
Measurements taken electrically with a two−pole RC filter
on the output with a cutoff frequency (−3 dB point) of 8 kHz.
From 2 kHz to 8 kHz, the roll−off is due to the RC filter.
14
2
C bus within
2
C interfaces:
2
C interface is a hardware debugger
2
C interface.
2
C
2
C interface is a
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