Huawei MU509 Series Design Manual page 15

HUAWEI LGA Module PCM Audio Design Guide
is powered up
{0x52,0x00},
{0x53,0x00},
//Playback Setup
{0x00,0x01},
{0x0C,0x08},
terminal is routed to HPL
{0x0D,0x01},
output is powered by AVDD)
0dB
{0x14,0x35},
time constants ( do not use for Rchg=25K)
6k resistance
{0x3F,0xD6},
Powered Up
Right DAC data Right Channel Audio Interface Data
not muted
};
Issue 04 (2016-12-12)
{0x00,0x00}, //Select Register 0
{0x51,0xC0}, //Left Channel ADC is powered up
//Left ADC Channel Un-muted
// Left ADC Channel Volume Control ADC gain=0dB
{0x09,0x3C},
//Left Channel DAC reconstruction filter's positive
//If you use LOR or LOL, you should change this value
//HPL output is routed to HPR (use when HPL and HPR
{0x10,0x00}, //HPL driver is not muted
{0x11,0x00}, // HPR driver is not muted
{0x12,0x00},
{0x13,0x00}, // LOR driver is not muted
//1101: Headphone ramps power up slowly in 16.0
//01: Headphone ramps power up time is determined with
//DAC configuration
{0x00,0x00},
//Left DAC Channel Powered Up
//Left DAC data Left Channel Audio Interface Data
//Soft-Stepping is disabled
{0x40,0x00}, //Left DAC Channel not muted
{0x41,0x08}, //Left DAC Channel Digital Volume Control Setting
{0x42,0x08}, //Right DAC Channel Digital Volume Control Setting
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//HPL、HPR、LOL、LOR is powered up
// LOL driver is not muted
Reference Design
Right Channel ADC
HPL driver gain is 0dB
HPR driver gain is 0dB
LOL driver gain is
LOR driver gain is 0dB
Right DAC Channel
Right DAC Channel
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