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Loongson 3A2000 User Manual

Volume one multi-core processor architecture, register description and system software programming guide
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4/29/2020
Godson 3A2000 / 3B2000 Processor User Manual
Page 1
Loongson 3A2000 / 3B2000 processor
User Manual
volume One
Multi-core processor architecture, register description and system software programming guide
V1.7
2017
Nian 02 Yue
Loongson Zhongke Technology Co., Ltd.
Page 2
Copyright Notice
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Summary of Contents for Loongson 3A2000

  • Page 1 4/29/2020 Godson 3A2000 / 3B2000 Processor User Manual Page 1 Loongson 3A2000 / 3B2000 processor User Manual volume One Multi-core processor architecture, register description and system software programming guide V1.7 2017 Nian 02 Yue Loongson Zhongke Technology Co., Ltd. Page 2...
  • Page 2 Godson 3A2000 / 3B2000 Processor User Manual The copyright of this document belongs to Loongson Zhongke Technology Co., Ltd. and reserves all rights. Without written permission, any company and individual No one may publicize, reprint or otherwise distribute any part of this document to third parties. Otherwise, the law will be investigated Legal responsibility.
  • Page 3 4/29/2020 Godson 3A2000 / 3B2000 Processor User Manual Page 4 revise history Godson 3A2000 / 3B2000 Processor User Manual Document name: --volume One V1.7 version number Document update record founder: Chip R & D Department Creation Date: 2017-02-14 Update history...

  • Page 4: Table Of Contents

    1.1 Introduction to Loongson series processors ................... 11 1.2 Introduction to Godson 3A2000 / 3B2000 .................. 12 1.3 Description of Loongson 3A2000 Commercial and Industrial Chips ..............14 2 System Configuration and Control ....................16 2.1 Chip working mode ..........
  • Page 5 Godson 3A2000 / 3B2000 Processor User Manual 9.5.1 Initialization ....................51 Page 6 Godson 3A2000 / 3B2000 processor user manual directory 9.5.2 Control of reset pin ................51 9.5.3 Leveling ....................53 9.5.3.1 Write Leveling ................53 9.5.3.2 Gate Leveling ..........
  • Page 6 11.3.7 Line Status Register (LSR) ..............110 11.3.8 MODEM Status Register (MSR) .............. 112 Page 8 Godson 3A2000 / 3B2000 processor user manual directory 11.3.9 Frequency Division Latch ..................112 11.4 SPI Controller ....................113 11.4.1 Control Register (SPCR) ..........

  • Page 7: Loongson 3A2000 / 3B2000 Processor

    Figure 9-1 DDR2 SDRAM read operation protocol ................47 Figure 9-2 DDR2 SDRAM write operation protocol ................47 Figure 10-1 HT protocol configuration access in Loongson 3A2000 .............. 97 Figure 10-2 Four-piece Loongson No. 3 interconnection structure ................. 98 Figure 10-3 Two-chip Loongson No.
  • Page 8 4/29/2020 Godson 3A2000 / 3B2000 Processor User Manual Page 10 Godson 3A2000 / 3B2000 Processor User Manual Table List Table directory Table 2-1 Control pin description ................... 16 Table 2-2 Node-level system global address distribution ................18 Table 2-3 Address distribution in nodes ..........
  • Page 9 Table 10-4 The default address window distribution of the four HyperTransport interfaces ........62 Table 10-5 Address window distribution inside HyperTransport interface of Loongson 3 processor ....63 Table 10-6 Address window provided in HyperTransport interface of Loongson 3A2000 processor 63 Table 10-7 Software visible register list ..........
  • Page 10 4/29/2020 Godson 3A2000 / 3B2000 Processor User Manual Godson 3A2000 / 3B2000 Processor User Manual Table List Table 10-29 HT Bus Interrupt Vector Register Definition (3) ............76 Table 10-30 HT Bus Interrupt Vector Register Definition (4) ............76 Table 10-31 Definition of HT Bus Interrupt Vector Register (6) ...........
  • Page 11 Table 11-5 Meaning of LPC Configuration Register ................105 Table 11-6 SPI controller address space distribution ................. 113 Table 11-6 IO Control Register ..................... 117 Table 11-7 Detailed description of registers ....................118 Page 14 Godson 3A2000 / 3B2000 Processor User Manual Table List...

  • Page 12: Overview

    Core 2 superscalar processor and its IP series are mainly for desktop applications, and Godson 3 multi-core processor series is mainly for service Server and high-performance machine applications. According to the needs of the application, some of Loongson 2 can also face some high-end embedded Yes, some low-end Loongson 3 can also be used for some desktop applications.

  • Page 13: Introduction To Godson 3A2000 / 3B2000

    Godson 3A2000 / 3B2000 Processor User Manual Figure 1-1 Loongson No. 3 system structure The structure of Loongson No. 3 node is shown in Figure 1-2 below. Each node has two levels of AXI crossbars connected to the processor and shared Page 16 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Cache, memory controller and IO controller.
  • Page 14 Support SPI start function; • Support full chip software frequency configuration; • The performance of the whole chip is optimized and improved. Godson 3A2000 Chip architecture is based on two integrally interconnected to achieve the following structure in FIG FIG. NODE CORE0 CORE1...

  • Page 15: Description Of Loongson 3A2000 Commercial And Industrial Chips

    GB 4937-1995 The Loongson 3A chip, like most semiconductor devices, has a failure rate that conforms to the bathtub curve model. Loongson 3A industrial grade chip In order to ensure longer-term, stable, and reliable operation, and to be able to adapt to more demanding environmental temperature requirements, the chip Reliability screening was conducted to eliminate early failure chips.

  • Page 16: System Configuration And Control

    ● Single chip mode. The system only contains one Loongson 3A2000, which is a symmetric multiprocessor system (SMP); ● Multi-chip interconnect mode. The system contains 2 pieces or 4 pieces Godson 3A2000, through the HT end of Godson 3A2000 It is a non-uniform memory access multiprocessor system (CC-NUMA);...
  • Page 17 2'b11 means the PHY clock is 2.4GHz Page 21 Godson 3A2000 / 3B2000 Processor User Manual Part 1 2'b00 indicates that the HT controller clock is divided by 8 of the PHY clock 2'b01 indicates that the HT controller clock is divided by 4 of the PHY clock...

  • Page 18: Cache Consistency

    2.3 Cache Loongson 3A2000 maintains the cache consistency between the processor and the I / O accessed through the HT port by hardware, but The hardware does not maintain the cache consistency of I / O devices connected to the system through PCI. During driver development, When PCI access devices perform DMA (Direct Memory Access) transmission, the software needs to perform Cache consistency maintain.

  • Page 19: Address Routing Distribution And Configuration

    0xFFF_FFFF_FFFF Unlike the mapping relationship of direction ports, Loongson 3A2000 can decide to share based on the actual application access behavior Cache cross-addressing mode. The 4 shared Cache modules in the node correspond to a total of 43 bits of address space, and each module The address space corresponding to the block is determined according to one of the two selection bits of the address bit, and can be dynamically configured and repaired by software change.
  • Page 20 0x3ff0_2090 CORE0_WIN2_MMAP 0x3ff0_2190 CORE1_WIN2_MMAP 0x3ff0_2098 CORE0_WIN3_MMAP 0x3ff0_2198 CORE1_WIN3_MMAP 0x3ff0_20a0 CORE0_WIN4_MMAP 0x3ff0_21a0 CORE1_WIN4_MMAP 0x3ff0_20a8 CORE0_WIN5_MMAP 0x3ff0_21a8 CORE1_WIN5_MMAP Page 25 Godson 3A2000 / 3B2000 Processor User Manual Part 1 0x3ff0_20b0 CORE0_WIN6_MMAP 0x3ff0_21b0 CORE1_WIN6_MMAP 0x3ff0_20b8 CORE0_WIN7_MMAP 0x3ff0_21b8 CORE1_WIN7_MMAP 0x3ff0_2200 CORE2_WIN0_BASE 0x3ff0_2300 CORE3_WIN0_BASE 0x3ff0_2208 CORE2_WIN1_BASE 0x3ff0_2308 CORE3_WIN1_BASE...
  • Page 21 0x3ff0_2608 HT0_WIN1_BASE 0x3ff0_2708 HT1_WIN1_BASE 0x3ff0_2610 HT0_WIN2_BASE 0x3ff0_2710 HT1_WIN2_BASE 0x3ff0_2618 HT0_WIN3_BASE 0x3ff0_2718 HT1_WIN3_BASE twenty one Page 26 Godson 3A2000 / 3B2000 Processor User Manual Part 1 0x3ff0_2620 HT0_WIN4_BASE 0x3ff0_2720 HT1_WIN4_BASE 0x3ff0_2628 HT0_WIN5_BASE 0x3ff0_2728 HT1_WIN5_BASE 0x3ff0_2630 HT0_WIN6_BASE 0x3ff0_2730 HT1_WIN6_BASE 0x3ff0_2638 HT0_WIN7_BASE 0x3ff0_2738 HT1_WIN7_BASE...
  • Page 22 4/29/2020 Godson 3A2000 / 3B2000 Processor User Manual Page 27 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Table 2-7 Correspondence between the slave device number and the module at the secondary XBAR Slave device number default No. 0 DDR2 / 3 controller No.
  • Page 23 3ff0 0158 PCI_WIN3_MASK PCI window 3 mask twenty four Page 29 Godson 3A2000 / 3B2000 Processor User Manual Part 1 3ff0 0160 PCI_WIN4_MASK PCI window 4 mask 3ff0 0168 PCI_WIN5_MASK PCI window 5 mask 3ff0 0170 PCI_WIN6_MASK Mask of PCI window 6...

  • Page 24: Chip Configuration And Sampling Register

    0x0000_0000_1000_0000 0x0000_0000_1FFF_FFFF 2.6 Chip configuration and sampling register The chip configuration register (Chip_config) and chip sampling register (Chip_sample) in Loongson 3A2000 provide A mechanism to read and write the configuration of the chip. Page 30 Godson 3A2000 / 3B2000 Processor User Manual Part 1...
  • Page 25 103: 96 Thsens0_out Junction temperature = Thens0_out -100 Temperature range -40 degrees – 125 degrees Page 31 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Temperature sensor 1 Celsius 111: 104 Thsens1_out Junction temperature = Thens1_out -100 Temperature range -40 degrees – 125 degrees...
  • Page 26 4/29/2020 Godson 3A2000 / 3B2000 Processor User Manual Page 32 Godson 3A2000 / 3B2000 Processor User Manual Part 1 38:32 L1_DIV_LOOPC L1 PLL input parameters 41:39- 47:42 L1_DIV_OUT L1 PLL input parameters Other- Keep Note: PLL ouput = (clk_ref * div_loopc) / div_out.

  • Page 27: Gs464E Processor Core

    Applications and desktop applications can also be used as basic processor cores to form on-chip multi-core systems for server and high-performance applications use. Multiple GS464 cores and shared Cache modules in Loongson 3A2000 form one through AXI interconnection network Multi-core structure of distributed shared on-chip last-level cache. The main features of GS464 are as follows: •...
  • Page 28 The structure of GS464e is shown in the figure below. For more detailed introduction, please refer to the GS464e user manual and MIPS64 user manual. Page 35 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Exception bus Commit bus...

  • Page 29: Shared Cache (Scache)

    Page 36 Godson 3A2000 / 3B2000 Processor User Manual Part 1 4 Shared Cache (SCache) The SCache module is a three-level cache shared by all processor cores within the Loongson 3A2000 processor. SCache module The main features include: • Using 128-bit AXI interface.

  • Page 30: Matrix Processing Accelerator

    4/29/2020 Godson 3A2000 / 3B2000 Processor User Manual Page 37 Godson 3A2000 / 3B2000 Processor User Manual Part 1 RAM. Table 4-1 Shared Cache Lock Window Register Configuration name address Bit field description Slock0_valid 0x3ff00200 [63:63] Lock window 0 valid bits...
  • Page 31 The configuration of the matrix realizes the function of transposing or moving the matrix stored in the memory from the source matrix to the target matrix. Two The accelerators are integrated in the two HyperTransport controllers of Loongson 3A2000, which are realized by a first-level cross switch Read and write to SCache and memory.
  • Page 32 19..16 Awcache, write command internal control bit. When it is 4'hf, the cache path is used, and when it is 4'h0, the uncache path is used. other Page 40 Godson 3A2000 / 3B2000 Processor User Manual Part 1 The value is meaningless.
  • Page 33 6 Inter-processor interrupt and communication Godson 3A2000 implements 8 inter-core interrupt registers (IPI) for each processor core to support multi-core BIOS boot Interrupt and communication between the processor cores when the mobile and operating system are running. For descriptions and addresses, see Table 6-1 to Table 6-5.
  • Page 34 IPI_MailBox3 register of processor core 3 Listed above are the inter-core interrupt related messages for a single-node multiprocessor system composed of a single Loongson 3A2000 chip Memory list. When using multiple Loongson 3A2000 interconnects to form a multi-node CC-NUMA system, the node pairs in each chip...

  • Page 35: O Interrupt

    7 I / O interrupt Loongson 3A2000 chip supports up to 32 interrupt sources, which are managed in a unified manner, as shown in Figure 7-1 below, any An IO interrupt source can be configured as enabled, triggered, and routed to the processor core interrupt pin.
  • Page 36 Enabled situation. The interrupt signal in the form of pulse (such as PCI_SERR) is selected by the Intedge configuration register, write 1 Page 45 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Display pulse trigger, write 0 to indicate level trigger. The interrupt handler can clear the pulse record through the corresponding bit of Intenclr record.
  • Page 37 0x3ff01458 Four processor cores are integrated in Loongson 3A2000. The above 32-bit interrupt sources can be selected through software configuration. The target processor core is expected to be interrupted. Further, the interrupt source can be selected to route to any of the processor core interrupts Meaning one, that is, IP2 to IP5 corresponding to CP0_Status.

  • Page 38: Temperature Sensor

    8.1 Real-time temperature sampling Loongson 3A2000 integrates two temperature sensors internally, which can be performed through the sampling register starting at 0x1FE00198 Observation, at the same time, can use the flexible high and low temperature interrupt alarm or automatic frequency modulation function to control. Temperature sensor in...

  • Page 39: High Temperature Automatic Frequency Reduction Setting

    EN: interrupt enable control. The setting of this group of registers is valid after being set to 1; SEL: Input temperature selection. Currently 3A2000 integrates two temperature sensors, this register is used for configuration selection The temperature of which sensor is used as input. You can use 0 or 1.

  • Page 40: Ddr2 / 3 Sdram Controller Configuration

    9 DDR2 / 3 SDRAM controller configuration The design of the integrated memory controller inside Loongson No. 3 processor complies with the industry standard of DDR2 / 3 SDRAM (JESD79-2 And JESD79-3). In the Godson 3 processor, all memory read / write operations are implemented in compliance with JESD79-2B and The provisions of JESD79-3.

  • Page 41: Ddr2 / 3 Sdram Read Operation Protocol

    RAS_n, CAS_n and WE_n are composed of three signals. For read operations, RAS_n = 1, CAS_n = 0, and WE_n = 1. Page 51 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Figure 9-1 DDR2 SDRAM read operation protocol In the figure above, Cas Latency (CL) = 3, Read Latency (RL) = 3, and Burst Length = 8.

  • Page 42: Ddr2 / 3 Sdram Parameter Configuration Format

    4/29/2020 Godson 3A2000 / 3B2000 Processor User Manual Page 52 Godson 3A2000 / 3B2000 Processor User Manual Part 1 9.4 DDR2 / 3 SDRAM parameter configuration format The parameter list and description of the memory controller software are as follows:...
  • Page 43 4/29/2020 Godson 3A2000 / 3B2000 Processor User Manual Godson 3A2000 / 3B2000 Processor User Manual Part 1 63:56 55:48 47:40 39:32 31:24 23:16 15: 8 7: 0 0x120 Dq_oe_end_8 Dq_oe_begin_8 Dq_stop_edge_8 Dq_start_edge_8 Rddata_delay_8 Rddqs_lt_half_8 Wrdqs_lt_half_8 Wrdq_lt_half_8 0x128 Rd_oe_end_8 Rd_oe_begin_8 Rd_stop_edge_8 Rd_start_edge_8 Dqs_oe_end_8...

  • Page 44: Software Programming Guide

    Ecc_cnt_cs_3 Ecc_cnt_cs_2 Ecc_cnt_cs_1 Ecc_cnt_cs_0 0x368 Page 55 Godson 3A2000 / 3B2000 Processor User Manual Part 1 9.5 Software Programming Guide Initial operation 9.5.1 The initialization operation is started when the software writes 1 to the register Init_start (0x018). Set Init_start Before the signal, all other registers must be set to the correct values.
  • Page 45 ● When the controller starts to initialize, the pin state is high; ● During normal operation, the pin status is high. The timing is shown below: Page 56 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Internal reset Software enable DLL lock POWER...

  • Page 46: Leveling

    4/29/2020 Godson 3A2000 / 3B2000 Processor User Manual ● Always low; The timing is shown below: Page 57 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Internal reset Software enable DLL lock POWER Sys_reset DDR_RESETn Particle RESETn By the combination of the latter two reset modes, it can be realized directly using the reset signal of the memory controller STR control.

  • Page 47: Gate Leveling

    Godson 3A2000 / 3B2000 Processor User Manual Page 58 Godson 3A2000 / 3B2000 Processor User Manual Part 1 (8) Sampling Lvl_resp_x (0x180, 0x188) register, if it is 0, the corresponding Dll_wrdqs_x [6: 0] Increase 1 and repeat 5-7; if it is 1, it means that the Write Leveling operation has been successful;...

  • Page 48: Initiate Mrs Commands Separately

    (4) Write Mrs_req (0x198) to 1, send MRS command to DRAM; Page 60 Godson 3A2000 / 3B2000 Processor User Manual Part 1 (5) Sampling Mrs_done (0x198), if it is 1, it means that the MRS command has been sent and can be exited, If it is 0, you need to continue to wait;...

  • Page 49: Self-Loop Test Mode Control

    (4) The sampling register Dll_init_done (0x000), if this value is 1, it means that the DLL is locked and can Page 61 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Proceed to the next operation; if this value is 0, you need to continue to wait; (when using the test port for control When you do n’t see the output of this register, you do n’t need to sample this register, but only need to...

  • Page 50: Hypertransport Controller

    10 HyperTransport controller In Loongson 3A2000, the HyperTransport bus is used to connect external devices and interconnect multiple chips. Used outside When setting up the connection, the user program can freely choose whether to support IO Cache consistency (through the address window Uncache Settings, see Section 10.5.13 for details): When configured to support Cache consistency mode, the IO device accesses the internal DMA...
  • Page 51 4/29/2020 Godson 3A2000 / 3B2000 Processor User Manual Page 63 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Controlled by two independent controllers, the address space is divided into HT0_Lo: address [40] = 0; HT0_Hi: address [40] = 1;...

  • Page 52: Hypertransport Protocol Support

    The configuration of the device at the end needs to be one-to-one correspondence, otherwise the HyperTransport interface will not work properly. 10.2 HyperTransport protocol support Godson 3A2000's HyperTransport bus supports most commands in version 1.03 / 3.0 protocol, and is Some extended instructions have been added to the extended consistency protocol that supports multi-chip interconnection. In the above two modes, The commands that the HyperTransport receiver can receive are shown in the following table.

  • Page 53: Hypertransport Interrupt Support

    The corresponding interrupt on the controller. Only after the above four steps are completed, the PIC controller will issue the next interrupt to the system. for Loongson 3A2000 HyperTransport controller will automatically process the first 3 steps and write the PIC interrupt vector Corresponding position in 256 interrupt vectors.

  • Page 54: Hypertransport Space

    Godson 3A2000 / 3B2000 Processor User Manual HyperTransport space 10.4.1 In the Loongson 3A2000 processor, the default address windows of the four HyperTransport interfaces are distributed as follows: Table 10-4 Default address window distribution of the four HyperTransport interfaces Base address...

  • Page 55: Configuration Register

    4/29/2020 Godson 3A2000 / 3B2000 Processor User Manual Page 68 Godson 3A2000 / 3B2000 Processor User Manual Part 1 When the processor cores are executed out of order, the total Issue some guess read access or fetch Access, this access for some IO space...

  • Page 56: Bridge Control

    Used to manually set the size of the sender buffer (for debugging) Buffer debug register on the sending side Page 70 Godson 3A2000 / 3B2000 Processor User Manual Part 1 0x10C The PHY impedance matching configuration register is used to configure the impedance matching configuration of the PHY transmitter and receiver...

  • Page 57: Capability Registers

    31:29 HOST / Sec Command format is HOST / Sec 28:27 Reserved Keep Page 71 Godson 3A2000 / 3B2000 Processor User Manual Part 1 HOST / SLAVE mode Act as Slave R / W The initial value is determined by the pin HOSTMODE...
  • Page 58 Maximum width of HT bus receiving end: 16bits 15:14 Reserved Keep Page 72 Godson 3A2000 / 3B2000 Processor User Manual Part 1 LDTSTOP # When the HT bus enters the HT Disconnect state, is it off R / W Close HT PHY...
  • Page 59 4/29/2020 Godson 3A2000 / 3B2000 Processor User Manual Page 73 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Reset value: 0x00000002 Name: Feature Capability Table 10-12 Feature Capability register definition Bit field Bit field name Bit width reset value Visit description...

  • Page 60: Receive Diagnostic Register

    (1, 3, 5, 7) Four phases corresponding to CTL1 sampling 31:16 rx_cad_phase_0 twenty four R / W save the input CAD [15: 0] value obtained by sampling Page 75 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Interrupt routing mode selection register 10.5.5 Offset: 0x58 Reset value: 0x00000000...

  • Page 61: Receive Address Window Configuration Register

    Page 76 Godson 3A2000 / 3B2000 Processor User Manual Part 1 The command is forwarded back to the HT bus, and the HT address that falls within the normal receive window and is not in the P2P window will be sent to the CPU.
  • Page 62 Offset: 0x6c Reset value: 0x00000000 Page 77 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Name: HT bus receive address window 1 base address (external access) Table 10-20 HT bus receive address window 1 base address (external access) register definition...

  • Page 63: Interrupt Vector Register

    4/29/2020 Godson 3A2000 / 3B2000 Processor User Manual Page 78 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Bit field Bit field name Bit width reset value Visit description ht_rx_image3_ 29: 0 R / W HT bus receive address window 3, the translated address [53:24]...
  • Page 64 Table 10-27 HT Bus Interrupt Vector Register Definition (1) Bit field Bit field name Bit width reset value Visit description Page 80 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Bit field Bit field name Bit width reset value Visit description Interrupt_case...

  • Page 65: Interrupt Enable Register

    Corresponding to interrupt line 2 / HT HI Corresponding to interrupt line 6 Offset: 0x94 Page 81 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Reset value: 0x00000000 Name: HT Bus Interrupt Vector Register [191: 160] Table 10-31 HT bus interrupt vector register definition (6)
  • Page 66 [192,193,194,195 ... 255] corresponds to interrupt line 3 / HT HI corresponds to interrupt line 7 Page 82 Godson 3A2000 / 3B2000 Processor User Manual Part 1 ht_int_stripe_2: [0,2,4,6 …… 126] Corresponding to interrupt line 0 / HT HI Corresponding to interrupt line 4 [1,3,5,7 ...
  • Page 67 4/29/2020 Godson 3A2000 / 3B2000 Processor User Manual Page 83 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Table 10-36 Definition of HT Bus Interrupt Enable Register (3) Bit field Bit field name Bit width reset value access description...

  • Page 68: Interrupt Discovery & Configuration

    Bit field name Bit width reset value Visit description 31:24 IntrInfo [31:24] 0xF8 Keep Page 85 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Bit field Bit field name Bit width reset value Visit description 23: 2 IntrInfo [23: 2]...

  • Page 69: Post Address Window Configuration Register

    Reset value: 0x00000000 Name: HT bus POST address window 0 base address (internal access) Page 86 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Table 10-47 HT bus POST address window 0 base address (internal access) Bit field Bit field name...

  • Page 70: Prefetchable Address Window Configuration Register

    Is sent to the HT bus, other fetch instructions or CACHE access will not be sent to the HT bus, but will return immediately, if it is a read Command, it will return the corresponding number of invalid read data. Page 87 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Offset: 0xe0 Reset value: 0x00000000...

  • Page 71: Uncache Address Window Configuration Register

    Godson 3A2000 / 3B2000 Processor User Manual Bit field Bit field name Bit width reset value Visit description Page 88 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Bit field Bit field name Bit width reset value Visit description ht_prefetch1_...
  • Page 72 Name: HT bus Uncache address window 2 base address (internal access) Table 10-59 HT bus Uncache address window 2 base address (internal access) Page 90 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Bit field Bit field name Bit width reset value Visit description...

  • Page 73: P2P Address Window Configuration Register

    Reset value: 0x00000000 Name: HT bus P2P address window 0 enable (external access) Page 91 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Table 10-62 HT bus P2P address window 0 enable (external access) register definition Bit field Bit field name...

  • Page 74: Command Send Buffer Size Register

    Table 10-65 HT bus P2P address window 1 base address (external access) register definition Bit field Bit field name Bit width reset value Visit description Page 92 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Bit field Bit field name Bit width reset value Visit description 31:16 ht_p2p_image1_...

  • Page 75: Send Buffer Debug Register

    Send buffer debugging register is used to manually set the number of buffers at the sending end of the HT controller. Page 93 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Adjust the number of different send buffers. Offset: 0x108...

  • Page 76: Revision Id Register

    4/29/2020 Godson 3A2000 / 3B2000 Processor User Manual Godson 3A2000 / 3B2000 Processor User Manual Part 1 27:24 Tx_scanin_ncode 4 R / W TX impedance matching scan input ncode 23:20 Tx_scanin_pcode 4 R / W TX impedance matching scan input pcode...

  • Page 77: Link Train Register

    8: 7 Receiver LS select 2 R / W Link status: 2'b00 LS1 Page 96 Godson 3A2000 / 3B2000 Processor User Manual Part 1 2'b01 LS0 2'b10 LS2 2'b11 LS3 6: 4 Long Retry Count 3 R / W Long Retry...

  • Page 78: Training 0 Time-Out Timer Register

    Training 1 count register 10.5.25 Used in Training 1 counting threshold in HyerTransport 3.0 mode, the counter clock frequency is Page 97 Godson 3A2000 / 3B2000 Processor User Manual Part 1 HyperTransport3.0 link bus clock frequency is 1/4. Offset: 0x13C Reset value: 0x0004fffff...
  • Page 79 The specific switching method is: on the premise of enabling the software configuration mode, set the first bit of the software frequency configuration register, Page 98 Godson 3A2000 / 3B2000 Processor User Manual Part 1 And write the parameters related to the new clock, including div_refc and div_loop that determine the output frequency of the PLL.

  • Page 80: Phy Configuration Register

    4/29/2020 Godson 3A2000 / 3B2000 Processor User Manual Page 99 Godson 3A2000 / 3B2000 Processor User Manual Part 1 PHY Configuration Register 10.5.29 Used to configure PHY related physical parameters. When the controller is used as two independent 8bit controllers, the high-order The PHY and the lower PHY are independently controlled by two controllers;...

  • Page 81: Ldt Debug Register

    The underlying protocol is related, and the specific access details are slightly different. As listed in Table 10-5 , the address range of the HT bus configuration space It is 0xFD_FE00_0000 to 0xFD_FFFF_FFFF. For configuration access in HT protocol, it is adopted in Godson 3A2000 Implemented in the following format: Page 101...

  • Page 82: Hypertransport Multiprocessor Support

    HT0_ HT0_ 8-bit HT bus Figure 10-2 Four-piece Loongson No. 3 interconnection structure Loongson 3 interconnection routing Loongson No. 3 interconnection routing adopts simple XY routing method. When routing, X followed by Y, taking four chips as an example, ID...
  • Page 83 Due to the characteristics of this algorithm, we will adopt different methods when constructing the interconnection of two chips. Page 103 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Two piece Loongson No. 3 interconnection structure Due to the nature of the fixed routing algorithm, we have two different methods when constructing the interconnection of two chips. first of all Using 8-bit HT bus interconnection.

  • Page 84: Low Speed Io Controller Configuration

    11.1 PCI controller The PCI controller of Loongson 3 can be used as the main bridge to control the entire system, or it can work as a common PC device. On the PCI bus. Its implementation conforms to the PCI 2.3 specification. The PCI controller of Godson 3 also has a built-in PCI arbiter.
  • Page 85 8: 1 delay access 9: 2 delay visit 10: 3 delay visit 11: 4 delay visit Page 106 Godson 3A2000 / 3B2000 Processor User Manual Part 1 12: 5 delay visit 13: 6 delay visit 14: 7 delay visit 15: 8 delay visit...
  • Page 86 Read only 15 err_type Read only The wrong module 14 err_module Page 107 Godson 3A2000 / 3B2000 Processor User Manual Part 1 0: target 1: master Read and write 0 13 system_error Target / master system error (write 1 clear)
  • Page 87 11-1 Page 108 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Figure 11-1 Configure read and write bus address generation The PCI arbiter implements two-level round robin arbitration, bus docking, and isolation of damaged master devices. See its configuration and status PXArb_Config and PXArb_Status registers.

  • Page 88: Lpc Controller

    4/29/2020 Godson 3A2000 / 3B2000 Processor User Manual Page 109 Godson 3A2000 / 3B2000 Processor User Manual Part 1 11.2 LPC controller The LPC controller has the following characteristics: ● Conform to LPC1.1 specification ● Support LPC access timeout counter ●...

  • Page 89: Uart Controller

    The base address of the physical address of the UART0 register is 0x1FE001E0. The base address of the physical address of the UART1 register is 0x1FE001E8. Page 111 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Data Register ( DAT ) 11.3.1...

  • Page 90: Interrupt Identification Register (Iir)

    3: 1 Interrupt indication bit INTp Interrupt control function table Page 112 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Interrupt source Interrupt reset control Bit 3 Bit 2 Bit 1 Priority interrupt type Receive line status Parity, overflow, or frame error, or hit...

  • Page 91: Line Control Register (Lcr)

    Line Control Register ( LCR ) 11.3.5 Chinese name: Line Control Register Register bit width: [7: 0] Page 113 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Offset: 0x03 Reset value: 0x03 Bit field Bit field name Bit width access...

  • Page 92: Modem Control Register (Mcr)

    4/29/2020 Godson 3A2000 / 3B2000 Processor User Manual Page 114 Godson 3A2000 / 3B2000 Processor User Manual Part 1 '10' – 7 digits '11' – 8 digits MODEM control register ( MCR ) 11.3.6 Chinese name: Modem control register Register bit width: [7: 0]...

  • Page 93: Modem Status Register (Msr)

    '0' – No data in FIFO Page 116 Godson 3A2000 / 3B2000 Processor User Manual Part 1 '1' – There is data in the FIFO When reading this register, LSR [4: 1] and LSR [7] are cleared, and LSR [6: 5] is writing data to the transmit FIFO Cleared according to the time, LSR [0] judges the receive FIFO.

  • Page 94: Frequency Division Latch

    Bit field name Bit width access description Page 117 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Stores the upper 8 bits of the divider latch 7: 0 11.4 SPI controller The SPI controller has the following features: ● Full duplex synchronous serial data transmission ●...

  • Page 95: Control Register (Spcr)

    Interrupt output enable signal is high and effective Spie System work enable signal is highly effective Page 118 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Keep Reserved mstr master mode selection bit, this bit keeps 1 Clock polarity bit...
  • Page 96 4/29/2020 Godson 3A2000 / 3B2000 Processor User Manual Page 119 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Offset: 0x03 Reset value: 0x00 Bit field Bit field name Bit width access description Send an interrupt request signal after how many bytes are transferred...

  • Page 97: Timing Control Register (Sfc_Timing)

    10: 4T 11: 8T Page 121 Godson 3A2000 / 3B2000 Processor User Manual Part 1 11.5 IO controller configuration The configuration register is mainly used to configure the address window, arbiter and GPIO controller of the PCI controller. Table 11-6...
  • Page 98 Pre-fetch window mask high 32 bits Mem_Win_Mask_H PCI_Hit0_Sel_L PCI window 0 controls the lower 32 bits Page 122 Godson 3A2000 / 3B2000 Processor User Manual Part 1 PCI window 0 controls the upper 32 bits PCI_Hit0_Sel_H PCI_Hit1_Sel_L PCI Window 1 controls the lower 32 bits...
  • Page 99 Read-write 0 11: 6 trans_lo1 PCI_Mem_Lo1 window map address high 6 bits Page 123 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Read-write 0 PCI_Mem_Lo2 window map address high 6 bits 17:12 trans_lo2 Read only 0 31:18 Reserved...
  • Page 100 4/29/2020 Godson 3A2000 / 3B2000 Processor User Manual Page 124 Godson 3A2000 / 3B2000 Processor User Manual Part 1 01: 8 cycles 10: 32 cycles 11: 128 cycles Read and write 8'h01 Equipment in the first level 15: 8 level...

  • Page 101: Chip Configuration Register List

    CPU_WIN6_MASK 0x3ff00070 Mask of CPU window 6 CPU_WIN7_MASK 0x3ff00078 Mask of CPU window 7 Page 126 Godson 3A2000 / 3B2000 Processor User Manual Part 1 CPU_WIN0_MMAP 0x3ff00080 New base address of CPU window 0 0xf0 CPU_WIN1_MMAP 0x3ff00088 New base address of CPU window 1...
  • Page 102 4/29/2020 Godson 3A2000 / 3B2000 Processor User Manual Page 127 Godson 3A2000 / 3B2000 Processor User Manual Part 1 PCI_WIN3_MASK 0x3ff00158 Mask of PCI window 3 PCI_WIN4_MASK 0x3ff00160 Mask of PCI window 4 PCI_WIN5_MASK 0x3ff00168 Mask of PCI window 5...
  • Page 103 4/29/2020 Godson 3A2000 / 3B2000 Processor User Manual MTX0_DST_START_ADDR 0x3ff00608 MTX0_ORI_LENTH 0x3ff00610 MTX0_ORI_WIDTH 0x3ff00618 MTX0_SRC_ROW_STRIDE 0x3ff00620 Page 129 Godson 3A2000 / 3B2000 Processor User Manual Part 1 MTX0_DST_ROW_STRIDE 0x3ff00628 MTX0_TRANS_CTRL 0x3ff00630 MTX1_SRC_START_ADDR 0x3ff00700 MTX1_DST_START_ADDR 0x3ff00708 MTX1_ORI_LENTH 0x3ff00710 MTX1_ORI_WIDTH 0x3ff00718 MTX1_SRC_ROW_STRIDE...
  • Page 104 0x3ff00A38 SCache3_perfctrl0 0x3ff00B00 SCache3_perfcnt0 0x3ff00B08 SCache3_perfctrl1 0x3ff00B10 SCache3_perfcnt1 0x3ff00B18 SCache3_perfctrl2 0x3ff00B20 Page 131 Godson 3A2000 / 3B2000 Processor User Manual Part 1 SCache3_perfcnt2 0x3ff00B28 SCache3_perfctrl3 0x3ff00B30 SCache3_perfcnt3 0x3ff00B38 Core0_IPI_Status 0x3ff01000 IPI_Status register of processor core 0 Core0_IPI_Enalbe 0x3ff01004 IPI_Enalbe register of processor core 0...
  • Page 105 0x3ff0130c IPI_Clear register of processor core 3 Core3_MailBox0 0x3ff01320 IPI_MailBox0 register of processor core 3 Page 133 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Core3_MailBox1 0x3ff01328 IPI_MailBox1 register of processor core 3 Core3_MailBox2 0x3ff01330 IPI_MailBox2 register of processor core 3...
  • Page 106 Godson 3A2000 / 3B2000 Processor User Manual Page 134 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Temperature sensor high temperature interrupt control register [7: 0]: Hi_gate0: high temperature threshold 0, an interrupt will be generated if this temperature is exceeded...
  • Page 107 Godson 3A2000 / 3B2000 Processor User Manual Page 136 Godson 3A2000 / 3B2000 Processor User Manual Part 1 Temperature sensor high-temperature down-frequency control register, four sets of setting priority from high to low [7: 0]: Scale_gate0: High temperature threshold 0, frequency will be reduced if this temperature is exceeded...
  • Page 108 0x3ff01800 [49]: awready Page 138 Godson 3A2000 / 3B2000 Processor User Manual Part 1 CORE0 AXI interface AW trigger enable 0 is set, the highest bit is AW channel trigger enable [49: 0]: awmask [62]: awdata_en: trigger is allowed only when the wdata trigger condition of the same wid is met at the same time...
  • Page 109 [63]: archannel_en: enable trigger condition CORE0_ARCOND1 0x3ff01830 [47: 0]: araddr CORE0_ARMASK1 0x3ff01838 Page 140 Godson 3A2000 / 3B2000 Processor User Manual Part 1 CORE0's AXI interface W trigger condition, similar to AW [15: 0]: wid [31:16]: wstrb [32]: wlast [33]: wvalid CORE0_WCOND0...
  • Page 110 4/29/2020 Godson 3A2000 / 3B2000 Processor User Manual Page 141 Godson 3A2000 / 3B2000 Processor User Manual Part 1 CORE0's AXI interface B trigger enable 0 setting, the highest bit is the B channel trigger enable [19: 0]: bmask CORE0_BMASK0...
  • Page 111 4/29/2020 Godson 3A2000 / 3B2000 Processor User Manual Page 143 Godson 3A2000 / 3B2000 Processor User Manual Part 1 CORE1 AXI interface AW trigger enable 0 is set, the highest bit is AW channel trigger enable The trigger condition is...
  • Page 112 [23]: reset_g [24]: stop [25]: start TUD1_CONF1 0x3ff019e8 [26]: cg_en Page 145 Godson 3A2000 / 3B2000 Processor User Manual Part 1 TUD1_RESULT 0x3ff019f0 TUD1 result register CORE2_AWCOND0 0x3ff01a00 CORE2 AXI interface AW trigger condition 0 setting CORE2's AXI interface AW trigger enable 0 setting, the highest bit is AW channel trigger enable...
  • Page 113 0x3ff01aa8 TUD2 configuration register 0 [47: 0]: count_target TUD2_CONF0 0x3ff01ae0 [55:48]: monitor_enable Page 147 Godson 3A2000 / 3B2000 Processor User Manual Part 1 TUD0 configuration register 1 [2: 0]: DCDL_sel_signal [5: 3]: DCDL_sel_clock [9: 6]: signal_sel [13:10]: clok_sel [20:14]: reading_sel...
  • Page 114 4/29/2020 Godson 3A2000 / 3B2000 Processor User Manual Page 148 Godson 3A2000 / 3B2000 Processor User Manual Part 1 CORE3_ARCOND0 0x3ff01b20 CORE3's AXI interface AR trigger condition, similar to AW CORE3_ARMASK0 0x3ff01b28 CORE3_ARCOND1 0x3ff01b30 CORE3_ARMASK1 0x3ff01b38 CORE3_WCOND0 0x3ff01b40 CORE3's AXI interface W trigger condition, similar to AW...
  • Page 115 4/29/2020 Godson 3A2000 / 3B2000 Processor User Manual TUD4_CONF0 0x3ff01ce0 [55:48]: monitor_enable Page 150 Godson 3A2000 / 3B2000 Processor User Manual Part 1 TUD4 configuration register 1 [2: 0]: DCDL_sel_signal [5: 3]: DCDL_sel_clock [8: 6]: signal_sel [11: 9]: clock_sel [18:12]: reading_sel...
  • Page 116 0x3ff01e10 The trigger condition of AW must be satisfied by both COND0 and COND1 HT0_AWMASK1 0x3ff01e18 Page 152 Godson 3A2000 / 3B2000 Processor User Manual Part 1 HT0_ARCOND0 0x3ff01e20 HT0's AXI interface AR trigger condition, similar to AW HT0_ARMASK0 0x3ff01e28...
  • Page 117 HT1's AXI interface B trigger condition, similar to AW HT1_BMASK0 0x3ff01f78 HT1_RCOND0 0x3ff01f80 HT1's AXI interface R trigger condition, similar to AW HT1_RMASK0 0x3ff01f88 Page 154 Godson 3A2000 / 3B2000 Processor User Manual Part 1 HT1_RCOND1 0x3ff01f90 HT1_RMASK1 0x3ff01f98 HT1_RCOND2 0x3ff01fa0 HT1_RMASK2 0x3ff01fa8...
  • Page 118 4/29/2020 Godson 3A2000 / 3B2000 Processor User Manual Page 155 Godson 3A2000 / 3B2000 Processor User Manual Part 1 CORE0_WIN7_MASK 0x3ff02078 First-level crossbar address window CORE0_WIN0_MMAP 0x3ff02080 First-level crossbar address window CORE0_WIN1_MMAP 0x3ff02088 First-level crossbar address window CORE0_WIN2_MMAP 0x3ff02090 First-level crossbar address window...
  • Page 119 4/29/2020 Godson 3A2000 / 3B2000 Processor User Manual Page 157 Godson 3A2000 / 3B2000 Processor User Manual Part 1 CORE2_WIN5_BASE 0x3ff02228 First-level crossbar address window CORE2_WIN6_BASE 0x3ff02230 First-level crossbar address window CORE2_WIN7_BASE 0x3ff02238 First-level crossbar address window CORE2_WIN0_MASK 0x3ff02240 First-level crossbar address window...
  • Page 120 First-level crossbar address window CORE3_WIN1_MMAP 0x3ff02388 First-level crossbar address window CORE3_WIN2_MMAP 0x3ff02390 First-level crossbar address window Page 159 Godson 3A2000 / 3B2000 Processor User Manual Part 1 CORE3_WIN3_MMAP 0x3ff02398 First-level crossbar address window CORE3_WIN4_MMAP 0x3ff023a0 First-level crossbar address window CORE3_WIN5_MMAP...
  • Page 121 First-level crossbar address window SOUTH_WIN7_BASE 0x3ff02538 First-level crossbar address window SOUTH_WIN0_MASK 0x3ff02540 First-level crossbar address window Page 161 Godson 3A2000 / 3B2000 Processor User Manual Part 1 SOUTH_WIN1_MASK 0x3ff02548 First-level crossbar address window SOUTH_WIN2_MASK 0x3ff02550 First-level crossbar address window SOUTH_WIN3_MASK...
  • Page 122 4/29/2020 Godson 3A2000 / 3B2000 Processor User Manual Godson 3A2000 / 3B2000 Processor User Manual Part 1 WEST_WIN4_BASE 0x3ff02620 First-level crossbar address window WEST_WIN5_BASE 0x3ff02628 First-level crossbar address window WEST_WIN6_BASE 0x3ff02630 First-level crossbar address window WEST_WIN7_BASE 0x3ff02638 First-level crossbar address window...

  • Page 123: Software And Hardware Design Guidelines

    13 Software and Hardware Design Guidelines Loongson 3A2000 processor pins are downward compatible with Loongson 3A1000 processor, but the corresponding software and hardware need to be carried out Configuration changes to enable the original compatibility mode, or open some new features of Godson 3A2000, this chapter focuses on Compared with the Godson 3A1000, the software and hardware settings of the Godson 3A2000 processor are different.

  • Page 124: Pmon Change Guide

    13.2 Frequency setting instructions In order to be basically compatible with the frequency configuration of Godson 3A1000, the hardware frequency configuration range of Godson 3A2000 is narrow. To obtain a wider frequency range and better clock quality, the software configuration in PMON is mainly used in Godson 3A2000 The configuration method is the same as Loongson 3B1500.

  • Page 125: Guidelines For Kernel Changes

    6. Use code similar to 3B1500 to configure processor core, memory and node PLL; Page 167 Godson 3A2000 / 3B2000 Processor User Manual Part 1 7. Use the memory controller configuration and parameter training code similar to 3B1500; 8. If HT works in 1.0 mode, HT can only work in 8-bit mode;...
  • Page 126 Godson 3A2000 / 3B2000 Processor User Manual Page 168 Godson 3A2000 / 3B2000 Processor User Manual Part 1 When the Uncache request occurs, the contents of the store fill buffer have been written back to the Cache; the second is that all The unlock operation in the synchronous operation shared between different cores is implemented using LL / SC instructions;...

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