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Loongson 3A3000 User Manual

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4/29/2020
Loongson 3A3000 / 3B3000 Processor User Manual
Page 1
Loongson 3A3000 / 3B3000 processor
User Manual
volume One
Multi-core processor architecture, register description and system software programming guide
V1.3
2017
Nian 4 Yue
Loongson Zhongke Technology Co., Ltd.
Page 2
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  • Page 1 4/29/2020 Loongson 3A3000 / 3B3000 Processor User Manual Page 1 Loongson 3A3000 / 3B3000 processor User Manual volume One Multi-core processor architecture, register description and system software programming guide V1.3 2017 Nian 4 Yue Loongson Zhongke Technology Co., Ltd. Page 2...
  • Page 2 Loongson 3A3000 / 3B3000 Processor User Manual The copyright of this document belongs to Loongson Zhongke Technology Co., Ltd. and reserves all rights. Without written permission, any company and individual No one may publicize, reprint or otherwise distribute any part of this document to third parties. Otherwise, the law will be investigated Legal responsibility.
  • Page 3 4/29/2020 Loongson 3A3000 / 3B3000 Processor User Manual Page 4 revise history Loongson 3A3000 / 3B3000 Processor User Manual Document name: --volume One V1.3 version number Document update record founder: Chip R & D Department Creation Date: 2017-04-13 Update history...

  • Page 4: Table Of Contents

    1 Overview.......................... 11 1.1 Introduction to Loongson series processors ................... 11 1.2 Introduction to Godson 3A3000 / 3B3000 ..................12 2 System Configuration and Control ....................15 2.1 Chip working mode ....................15 2.2 Description of control pins ........
  • Page 5 Loongson 3A3000 / 3B3000 Processor User Manual 9.5.3.1 Write Leveling ................53 Page 6 Godson 3A3000 / 3B3000 processor user manual directory 9.5.3.2 Gate Leveling ................54 9.5.4 Initiate MRS commands separately ................55 9.5.5 Arbitrary operation control bus ................. 56 9.5.6 Self-loop test mode control ..........
  • Page 6 11.4.1 Control Register (SPCR) ................. 114 11.4.2 Status Register (SPSR) ..............115 Page 8 Godson 3A3000 / 3B3000 processor user manual directory 11.4.3 Data Register (TxFIFO) ................115 11.4.4 External Register (SPER) ................. 115 11.4.5 Parameter control register (SFC_PARAM) ............116 11.4.6 Chip Select Control Register (SFC_SOFTCS) ..........
  • Page 7 Figure 9-1 DDR2 SDRAM read operation protocol ................... 47 Figure 9-2 DDR2 SDRAM write operation protocol ................... 47 Figure 10-1 HT protocol configuration access in Loongson 3A3000 / 3B3000 ........... 98 Figure 10-2 Four-piece Loongson No. 3 interconnection structure ................. 99 Figure 10-3 Two-chip Loongson No.
  • Page 8 4/29/2020 Loongson 3A3000 / 3B3000 Processor User Manual Page 10 Godson 3A3000 / 3B3000 processor user manual table of contents Table directory Table 2-1 Control pin description ................... 15 Table 2-2 Node-level system global address distribution ................17 Table 2-3 Address distribution in nodes ..........
  • Page 9 Table 10-5 Address window distribution inside HyperTransport interface of Loongson No. 3 processor ....63 Table 10-6 Address window provided in HyperTransport interface of Loongson 3A3000 / 3B3000 processor ... 63 Table 10-7 Software visible register list ................. 64 Table 10-8 Bus Reset Control Register Definition ..........
  • Page 10 4/29/2020 Loongson 3A3000 / 3B3000 Processor User Manual Godson 3A3000 / 3B3000 processor user manual table of contents Table 10-29 HT Bus Interrupt Vector Register Definition (3) ............... 77 Table 10-30 HT Bus Interrupt Vector Register Definition (4) ............... 77 Table 10-31 HT Bus Interrupt Vector Register Definition (6) ...........
  • Page 11 Table 11-5 Meaning of LPC Configuration Register ................. 106 Table 11-6 SPI controller address space distribution ................ 114 Table 11-7 IO Control Register ..................... 118 Table 11-8 Detailed description of registers ..................119 Page 14 Godson 3A3000 / 3B3000 processor user manual table of contents...

  • Page 12: Overview

    Core 2 superscalar processor and its IP series are mainly for desktop applications, and Godson 3 multi-core processor series is mainly for service Server and high-performance machine applications. According to the needs of the application, some of Loongson 2 can also face some high-end embedded applications, Some low-end Loongson 3 can also be used for some desktop applications.

  • Page 13: Introduction To Godson 3A3000 / 3B3000

    Loongson 3A3000 / 3B3000 Processor User Manual Figure 1-1 Loongson No. 3 system structure The structure of Loongson No. 3 node is shown in Figure 1-2 below. Each node has two levels of AXI crossbars connected to the processor and shared Page 16 Godson 3A3000 / 3B3000 Processor User Manual •...
  • Page 14 The performance of the whole chip is optimized and improved. The overall architecture of Loongson 3A3000 / 3B3000 chip is based on two-level interconnection. The structure is shown in Figures 1-3 below. Figure 1-3 Loongson 3A3000 / 3B3000 chip structure The first level interconnection uses a 6x6 crossbar switch, which is used to connect four GS464e cores (as a master device) and four shares Cache module (as a slave device), and two IO ports (each port uses a Master and a Slave).

  • Page 15: System Configuration And Control

    According to the structure of the system, Loongson 3A3000 / 3B3000 mainly includes three working modes: ● Single chip mode. The system contains only one Loongson 3A3000 / 3B3000, which is a symmetric multiprocessor system (SMP); ● Multi-chip interconnect mode. The system contains 2 or 4 Loongson 3A3000 / 3B3000, through Loongson The HT ports of 3A3000 / 3B3000 are interconnected, which is a non-uniform memory multiprocessor system (CC-NUMA) ●...
  • Page 16 2'b11 means the PHY clock is 2.4GHz Page 20 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 2'b00 indicates that the HT controller clock is divided by 8 of the PHY clock 2'b01 indicates that the HT controller clock is divided by 4 of the PHY clock...

  • Page 17: Cache Consistency

    2.3 Cache Loongson 3A3000 / 3B3000 maintains the cache between the processor and the I / O accessed through the HT port It is consistent, but the hardware does not maintain the cache consistency of the I / O devices connected to the system through PCI. During driver development, When DMA (Direct Memory Access) transmission is performed on a device connected via PCI, the software needs to perform Cache Consistency maintenance.

  • Page 18: Address Routing Distribution And Configuration

    2.5 Distribution of physical address space within a node The default distribution of the internal 44-bit physical address of each node of Loongson 3A3000 / 3B3000 processor is shown in the following table: Table 2-2 44-bit physical address distribution in the node...
  • Page 19 Loongson 3A3000 / 3B3000 Processor User Manual The routing of Loongson 3A3000 / 3B3000 is mainly realized through the two-stage crossbar of the system. First-level crossbar can Each Master port receives requests for routing configuration, each Master port has 8 address windows, you can Complete target routing in 8 address windows.
  • Page 20 0x3ff0_2270 CORE2_WIN6_MASK 0x3ff0_2370 CORE3_WIN6_MASK 0x3ff0_2278 CORE2_WIN7_MASK 0x3ff0_2378 CORE3_WIN7_MASK 0x3ff0_2280 CORE2_WIN0_MMAP 0x3ff0_2380 CORE3_WIN0_MMAP Page 25 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 0x3ff0_2288 CORE2_WIN1_MMAP 0x3ff0_2388 CORE3_WIN1_MMAP 0x3ff0_2290 CORE2_WIN2_MMAP 0x3ff0_2390 CORE3_WIN2_MMAP 0x3ff0_2298 CORE2_WIN3_MMAP 0x3ff0_2398 CORE3_WIN3_MMAP 0x3ff0_22a0 CORE2_WIN4_MMAP 0x3ff0_23a0 CORE3_WIN4_MMAP...
  • Page 21 Page 26 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 There are configuration register address space, DDR2 address space, and PCI address space in the second-level XBAR of Godson 3 There are three IP-related address spaces. The address window is for the CPU and PCI-DMA two IPs with master device functions It is set for routing and address translation.
  • Page 22 4/29/2020 Loongson 3A3000 / 3B3000 Processor User Manual Page 27 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 3ff0 0000 CPU_WIN0_BASE CPU window 0 base address 3ff0 0008 CPU_WIN1_BASE CPU window 1 base address 0x1000_0000 3ff0 0010 CPU_WIN2_BASE CPU window 2 base address...

  • Page 23: Chip Configuration And Sampling Register

    Low-speed I / O (PCI, etc.) 2.7 Chip configuration and sampling register Chip configuration register (Chip_config) and chip sampling register in Godson 3A3000 / 3B3000 (Chip_sample) provides a mechanism to read and write the configuration of the chip. Table 2-11 Chip Configuration Register (Physical Address 0x1fe00180)
  • Page 24 127: 96 Pad1v8_ctrl 6'h780 1v8 pad control other Keep Table 2- 12 Chip sampling register (physical address 0x1fe00190) Page 30 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 Bit field Field name access Reset value description 31: 0...
  • Page 25 Wait for the lock signal LOCKED_ * in the register to be 1; Set SEL_PLL_ * to 1, and the corresponding clock frequency will be switched to the frequency set by the software. In 3A3000 / 3B3000, two different PLLs can be used L1 L2 al_m 耀...
  • Page 26 4/29/2020 Loongson 3A3000 / 3B3000 Processor User Manual Page 32 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 127: 126 BBMUX_SEL_3 BBMUX_SEL_3 setting value other Keep Note: PLL ouput = (clk_ref * div_loopc) / div_out. The VCO frequency of the L1 PLL (the part in parentheses in the above formula) must be in the range 1.2GHz-3.2GHz. Should be It is also applicable to MEM PLL and HT PLL.

  • Page 27: Gs464E Processor Core

    Applications and desktop applications can also be used as basic processor cores to form on-chip multi-core systems for server and high-performance applications use. Multiple GS464 cores in Loongson 3A3000 / 3B3000 and shared cache modules are formed via AXI interconnection network It is a multi-core structure with a distributed shared on-chip last-level cache.
  • Page 28 The structure of GS464e is shown in the figure below. GS464e For more detailed introduction, please refer to GS464e user manual and MIPS64 User manual. Page 35 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 Figure 3- 1 GS464e structure diagram...

  • Page 29: Shared Cache (Scache)

    Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 4 Shared Cache (SCache) The SCache module is a three-level cache shared by all processor cores within the Loongson 3A3000 / 3B3000 processor. The main features of the SCache module include: •...

  • Page 30: Matrix Processing Accelerator

    4/29/2020 Loongson 3A3000 / 3B3000 Processor User Manual Page 37 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 Table 4- 1 Shared Cache Lock Window Register Configuration name address Bit field description Sl Yaock0_val d 0x3ff00200 [63:63] Lock window 0 valid bits...
  • Page 31 Loongson 3A3000 / 3B3000 Processor User Manual Godson 3A3000 / 3B3000 has built-in two matrix processing accelerators independent of the processor core. Its basic functions are Through the configuration of the software, the function of transposing or moving the matrix stored in the memory from the source matrix to the target matrix can be realized.
  • Page 32 19..16 Awcache, write command internal control bit. When it is 4'hf, the cache path is used, and when it is 4'h0, the uncache path is used. other Page 40 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 The value is meaningless.
  • Page 33 6 Inter-processor interrupt and communication Godson 3A3000 / 3B3000 implements 8 inter-core interrupt registers (IPI) for each processor core to support multiple core Interrupt and communication between the processor cores during BIOS startup and operating system operation, the description and addresses are shown in Table 6-1 to Table 6-5.
  • Page 34 Listed above is the inter-core of a single-node multi-processor system composed of a single Loongson 3A3000 / 3B3000 chip Break the relevant register list. When using multiple Loongson 3A3000 / 3B3000 interconnections to form a multi-node CC-NUMA system, each Page 43 Godson 3A3000 / 3B3000 Processor User Manual •...

  • Page 35: O Interrupt

    7 I / O interrupt Loongson 3A3000 / 3B3000 chip supports up to 32 interrupt sources and is managed in a unified manner, as shown in Figure 7-1 below Shows that any IO interrupt source can be configured to enable, trigger, and the target processor core to be routed...
  • Page 36 4/29/2020 Loongson 3A3000 / 3B3000 Processor User Manual Figure 7- 1 Schematic diagram of Loongson 3A3000 / 3B3000 processor interrupt routing Interrupt related configuration registers are used to control the corresponding interrupt lines in the form of bits. See Table 7-1 for sexual configuration. The interrupt enable (Enable) configuration has three registers: Intenset, Intenclr and Inten.
  • Page 37 32-bit interrupt status routed to CORE3 Four processor cores are integrated in Loongson 3A3000 / 3B3000, the above 32-bit interrupt sources can be configured by software Select the target processor core to be interrupted. Further, the interrupt source can be optionally routed to the processor core interrupt INT0 to INT3 Any one of the IP2 to IP5 corresponding to CP0_Status.

  • Page 38: Temperature Sensor

    EN: interrupt enable control. The setting of this group of registers is valid after being set to 1; SEL: Input temperature selection. At present, 3A3000 / 3B3000 integrate two temperature sensors inside, this register is used to configure The temperature of which sensor is selected as input. You can use 0 or 1.

  • Page 39: High Temperature Automatic Frequency Reduction Setting

    EN: interrupt enable control. The setting of this group of registers is valid after being set to 1; SEL: Input temperature selection. At present, 3A3000 / 3B3000 integrate two temperature sensors inside, this register is used to configure The temperature of which sensor is selected as input. You can use 0 or 1.

  • Page 40: Ddr2 / 3 Sdram Controller Configuration

    9 DDR2 / 3 SDRAM controller configuration The design of the integrated memory controller inside Loongson No. 3 processor complies with the industry standard of DDR2 / 3 SDRAM (JESD79-2 And JESD79-3). In the Godson 3 processor, all memory read / write operations are implemented in compliance with JESD79-2B and The provisions of JESD79-3.

  • Page 41: Ddr2 / 3 Sdram Read Operation Protocol

    CAS_n and WE_n are composed of three signals. For read operations, RAS_n = 1, CAS_n = 0, and WE_n = 1. Page 51 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 Figure 9- 1 DDR2 SDRAM read operation protocol In the figure above, Cas Latency (CL) = 3, Read Latency (RL) = 3, and Burst Length = 8.

  • Page 42: Ddr2 / 3 Sdram Parameter Configuration Format

    Loongson 3A3000 / 3B3000 Processor User Manual 9.4 DDR2 / 3 SDRAM parameter configuration format The parameter list and description of the memory controller software are as follows: Page 52 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 63:56 55:48 47:40...
  • Page 43 4/29/2020 Loongson 3A3000 / 3B3000 Processor User Manual Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 0x130 Enzi_end_8 Enzi_begin_8 Wrclk_sel_8 Wrdq_clkdelay_8 Odt_oe_end_8 Odt_oe_begin_8 Odt_stop_edge_8 Odt_start_edge_8 0x138 Enzi_stop_8 Enzi_start_8 Dll_oe_shorten_8Dll_rddqs_n_8 Dll_rddqs_p_8 Dll_wrdqs_8 Dll_wrdata_8 Dll_gate_8 0x140 Pad_ocd_clk Pad_ocd_ctl Pad_ocd_dqs Pad_ocd_dq...

  • Page 44: Software Programming Guide

    Zq_cnt_0 0x388 Zq_cnt_3 Zq_cnt_2 Page 55 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 9.5 Software Programming Guide Initial operation 9.5.1 The initialization operation is started when the software writes 1 to the register Init_start (0x018). Set Init_start Before the signal, all other registers must be set to the correct values.
  • Page 45 The timing is shown below: Page 56 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 (2) Reverse mode, reset_ctrl [1: 0] == 2'b10. In this mode, the reset signal pin is in memory In actual control, the effective level is opposite to the general control mode. So the DDR_RESETn needs to be Connect to the corresponding pin on the memory slot through the inverter.

  • Page 46: Leveling

    The timing is shown below: Page 57 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 By cooperating with the latter two reset modes, it is possible to realize STR directly using the reset signal of the memory controller control.

  • Page 47: Gate Leveling

    Loongson 3A3000 / 3B3000 Processor User Manual Page 58 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 (8) Sampling Lvl_resp_x (0x180, 0x188) register, if it is 0, the corresponding Dll_wrdqs_x [6: 0] Increase 1 and repeat 5-7; if it is 1, it means that the Write Leveling operation has been successful;...

  • Page 48: Initiate Mrs Commands Separately

    (5) Sampling Mrs_done (0x198), if it is 1, it means that the MRS command has been sent and can be exited, such as Page 60 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 If it is 0, you need to continue to wait;...

  • Page 49: Ecc Function Usage Control

    When you do n’t see the output of this register, you do n’t need to sample this register, but only need to Page 61 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 Wait here for a certain period of time to ensure that the DLL is locked, and then proceed to the next step);...

  • Page 50: Hypertransport Controller

    10 HyperTransport controller In Loongson 3A3000 / 3B3000, the HyperTransport bus is used to connect external devices and interconnect multiple chips. When used for peripheral connection, the user program can freely choose whether to support IO Cache consistency (through the address window Uncache Set, see section 10.5.13 for details): When configured to support Cache consistency mode, IO device accesses internal DMA...
  • Page 51 4/29/2020 Loongson 3A3000 / 3B3000 Processor User Manual Page 63 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 Controlled by two independent controllers, the address space is divided into HT0_Lo: address [40] = 0; HT0_Hi: address [40] = 1;...

  • Page 52: Hypertransport Protocol Support

    10.2 HyperTransport protocol support Godson 3A3000 / 3B3000's HyperTransport bus supports most commands in version 1.03 / 3.0 protocol, and In addition, some extended instructions are added to the extended consistency protocol that supports multi-chip interconnection. In the above two modes, The commands that the HyperTransport receiver can receive are shown in the following table.

  • Page 53: Hypertransport Interrupt Support

    The corresponding interrupt on the controller. Only after the above four steps are completed, the PIC controller will issue the next interrupt to the system. for Loongson 3A3000 / 3B3000 HyperTransport controller will automatically perform the first three steps of processing and interrupt the PIC to Write the corresponding position in the 256 interrupt vectors.

  • Page 54: Hypertransport Address Window

    10.4.1 HyperTransport space In the Loongson 3A3000 / 3B3000 processor, the default address windows of the four HyperTransport interfaces are distributed as follows: Table 10- 4 Address window distribution of the default 4 Hype, T, and Ansp interfaces Base address...

  • Page 55: Configuration Register

    4/29/2020 Loongson 3A3000 / 3B3000 Processor User Manual Page 68 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 After this write access will enter the processor Row write access complete response. When the processor cores are executed out of order, the total...

  • Page 56: Bridge Control

    0x100 Sender command buffer size register Sender buffer size register Page 70 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 0x104 Data buffer size register at the sending end 0x108 Used to manually set the size of the sender buffer (for debugging)

  • Page 57: Capability Registers

    Command format is HOST / Sec 28:27 Reserved Keep Page 71 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 HOST / SLAVE mode Act as Slave R / W The initial value is determined by the pin HOSTMODE...
  • Page 58 The maximum width of the sending end of the HT bus: 16bits Dw Fc In The receiver does not support double-word flow control Page 72 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 18:16 Max Link Width In Maximum width of HT bus receiving end: 16bits...
  • Page 59 4/29/2020 Loongson 3A3000 / 3B3000 Processor User Manual Page 73 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 HT bus operating frequency 11: 8 Link Freq R / W The value written to this register will be the next warm reset or HT...

  • Page 60: Receive Diagnostic Register

    The priority of each channel is changed according to time. High priority strategy, the group register is used to configure each channel 'S initial priority Page 75 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 Receive diagnostic register 10.5.4 Offset:...

  • Page 61: Interrupt Routing Mode Selection Register

    R / W Receive buffer read data buffer initialization information 23:20 rx_buffer_npc_data 4 R / W receive buffer npc data buffer initialization information Page 76 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 19:16 rx_buffer_pc_data R / W receive buffer pc data buffer initialization information 15:12...
  • Page 62 Table 10- 18 HT bus receive address window 0 base address (external access) register definition Bit field Bit field name Bit width reset value Visit description Page 77 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 Bit field Bit field name Bit width reset value Visit description ht_rx_image0_...
  • Page 63 4/29/2020 Loongson 3A3000 / 3B3000 Processor User Manual Page 78 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 Bit field Bit field name Bit width reset value Visit description ht_rx_image2_ 29: 0 R / W HT bus receive address window 2, the translated address [53:24]...

  • Page 64: Interrupt Vector Register

    [128,129,130,131 ... 191] Corresponding to interrupt line 2 / HT HI Corresponding to interrupt line 6 Page 80 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 [192,193,194,195 ... 255] corresponds to interrupt line 3 / HT HI corresponds to interrupt line 7 ht_int_stripe_2: [0,2,4,6 ……...
  • Page 65 Corresponding to interrupt line 0 / HT HI Corresponding to interrupt line 4 Offset: 0x88 Reset value: 0x00000000 Page 81 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 name: HT Bus Interrupt Vector Register [95:64] Table 10-29 HT Bus Interrupt Vector Register Definition (3) Bit field Bit field name...

  • Page 66: Interrupt Enable Register

    Table 10-32 HT Bus Interrupt Vector Register Definition (7) Bit field Bit field name Bit width reset value Visit description Page 82 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 Bit field Bit field name Bit width reset value Visit description Interrupt_case...
  • Page 67 Loongson 3A3000 / 3B3000 Processor User Manual Page 83 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 [2,6,10,14 ... 254] corresponds to interrupt line 2 / HT HI corresponds to interrupt line 6 [3,7,11,15 ... 255] corresponds to interrupt line 3 / HT HI corresponds to interrupt line 7 The following description of the interrupt vector corresponds to ht_int_stripe_1, and the other two methods can be obtained from the above description.

  • Page 68: Interrupt Discovery & Configuration

    31: 0 R / W [255: 224] Corresponding to interrupt line 3 / HT HI Corresponding to interrupt line 7 Page 85 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 Interrupt Discovery & Configuration 10.5.10 Offset: 0xc0 Reset value:...

  • Page 69: Post Address Window Configuration Register

    0x00000000 name: IntrInfo [63:32] Table 10-45 Int Yao Inf Yao register definition (2) Page 86 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 Bit field Bit field name Bit width reset value Visit description 31: 0 IntrInfo [63:32]...

  • Page 70: Prefetchable Address Window Configuration Register

    0x00000000 name: HT bus POST address window 1 enable (internal access) Page 87 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 Table 10-48 HT Bus POST Address Window 1 Enable (Internal Access) Bit field Bit field name Bit width reset value Visit description...

  • Page 71: Uncache Address Window Configuration Register

    4/29/2020 Loongson 3A3000 / 3B3000 Processor User Manual Page 88 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 ht_prefetch0_trans 15: 0 R / W HT bus can prefetch the address window 0, the translated address [39:24] [39:24] Offset:...
  • Page 72 Bit width reset value Visit description ht_uncache1_en R / W HT bus uncache address window 1, enable signal Page 90 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 ht_uncache1_ R / W HT bus uncache address window 1, mapping enable signal trans_en...
  • Page 73 31:16 R / W HT bus uncache address window 2, address base address [39:24] base [39:24] Page 91 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 Bit field Bit field name Bit width reset value Visit description ht_uncache1_...

  • Page 74: P2P Address Window Configuration Register

    HT bus P2P address window 0 enable (external access) Table 10-62 HT Bus P2P Address Window 0 Enable (External Access) Register Definition Page 92 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 Bit field Bit field name Bit width reset value Visit description...

  • Page 75: Command Send Buffer Size Register

    Table 10-65 HT bus P2P address window 1 base address (external access) register definition Bit field Bit field name Bit width reset value Visit description Page 93 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 Bit field Bit field name Bit width reset value Visit description 31:16...

  • Page 76: Phy Impedance Matching Control Register

    4/29/2020 Loongson 3A3000 / 3B3000 Processor User Manual Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 Adjust the number of different send buffers. Offset: 0x108 Reset value: 0x00000000 name: Send buffer debug register Table 10-68 Send Buffer Debug Register...

  • Page 77: Revision Id Register

    Retry Count Rollover Retry counter count rollover Reserved Keep Page 96 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 7: 6 Short Retry Attempts The maximum number of Short Retry allowed by R / W Retry Count register 10.5.21...

  • Page 78: Training 0 Timeout Short Timer Register

    22:21 Transmitter LS select 2 R / W The sending end is at Link status: 2'b00 LS1 Page 97 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 2'b01 LS0 2'b10 LS2 2'b11 LS3 In HyperTransport 3.0 mode, any 4 by default...

  • Page 79: Training 0 Time-Out Timer Register

    T0 time R / W Training 0 Timeout short timer register Page 98 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 Training 0 Time-out timer register 10.5.24 Used for Training 0 long counting timeout threshold in HyerTransport 3.0 mode, the counter clock frequency is HyperTransport3.0 link bus clock frequency is 1/4.
  • Page 80 4/29/2020 Loongson 3A3000 / 3B3000 Processor User Manual Page 99 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 HyperTransport3.0 link bus clock frequency is 1/4. Offset: 0x13C name: Training 3 count register Table 10- 78 T anan ng 3 count register...

  • Page 81: Phy Configuration Register

    1'b0 PLL clock 1'b1 external clock source 27:26 Rx_ctle_bitc R / W PAD EQD high frequency gain Page 101 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 25:24 Rx_ctle_bitr R / W PAD EQD low frequency gain 23:22 Rx_ctle_bitlim...

  • Page 82: Ldt Debug Register

    The underlying protocol is related, and the specific access details are slightly different. As listed in Table 10-5, the address range of the HT bus configuration space The range is 0xFD_FE00_0000 to 0xFD_FFFF_FFFF. For configuration access in the HT protocol, the Godson 3A3000 / 3B3000...
  • Page 83 Loongson 3 interconnection routing Loongson No. 3 interconnection routing adopts simple XY routing method. When routing, X followed by Y, taking four chips as an example, ID The numbers are 00, 01, 10, and 11, respectively. If you send a request from 11 to 00, it is a route from 11 to 00, first go in the X direction, Go from 11 to 10, then go in Y direction, and go from 10 to 00.

  • Page 84: Low Speed Io Controller Configuration

    11 Low-speed IO controller configuration Loongson No. 3 I / O controller includes PCI controller, LPC controller, UART controller, SPI controller, GPIO And configuration registers. These I / O controllers share an AXI port, and the CPU request is sent to the phase after address decoding...

  • Page 85: Pci Controller

    11.1 PCI controller The PCI controller of Loongson 3 can be used as the main bridge to control the entire system, or it can work as a common PC device. On the PCI bus. Its implementation conforms to the PCI 2.3 specification. The PCI controller of Godson 3 also has a built-in PCI arbiter.
  • Page 86 9: 2 delay visit 10: 3 delay visit 11: 4 delay visit Page 107 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 12: 5 delay visit 13: 6 delay visit 14: 7 delay visit 15: 8 delay visit...
  • Page 87 Read only _m 耀 dule Read only The wrong module Page 108 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 0: ta 1: maste Read and write 0 ta / get / maste / system error (write 1 clear) system_e 耀...

  • Page 88: Lpc Controller

    Loongson 3A3000 / 3B3000 Processor User Manual Page 109 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 Figure 11- 1 Configure read and write bus address generation The PCI arbiter implements two-level round robin arbitration, bus docking, and isolation of damaged master devices. See its configuration and status PXArb_Config and PXArb_Status registers.
  • Page 89 There are three 32-bit registers in the LPC controller configuration register. The meaning of the configuration register is shown in Table 11-5: Table 11- 5 LPC Configuration Register Meaning Page 111 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 Bit field Field name...

  • Page 90: Uart Controller

    The base address of the physical address of the UART0 register is 0x1FE001E0. The base address of the physical address of the UART1 register is 0x1FE001E8. Page 112 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 11.3.1 Data Register ( DAT )

  • Page 91: Fifo Control Register (Fcr)

    Interrupt source display bit, see the table below for details INTp Interrupt indication bit Interrupt control function table Page 113 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 Bit 3 Bit 2 Bit 1 Priority interrupt type Interrupt source...

  • Page 92: Modem Control Register (Mcr)

    4/29/2020 Loongson 3A3000 / 3B3000 Processor User Manual Page 114 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 0x03 Offset: 0x03 Reset value: Bit field Bit field name Bit width access description dlab Divider latch access bit '1'-access to the operation divider latch...

  • Page 93: Line Status Register (Lsr)

    Bit field Bit field name Bit width access description Page 116 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 ERROR Error indication bit '1'-at least parity error, framing error or interruption The broken one. '0' – no errors Transmission is empty '1' –...

  • Page 94: Modem Status Register (Msr)

    '0' – No data in FIFO Page 117 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 '1' – There is data in the FIFO When reading this register, LSR [4: 1] and LSR [7] are cleared, and LSR [6: 5] is writing data to the transmit FIFO Cleared according to the time, LSR [0] judges the receive FIFO.

  • Page 95: Spi Controller

    Bit field name Bit width access description Page 118 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 7: 0 Stores the upper 8 bits of the divider latch 11.4 SPI controller The SPI controller has the following features: ●...

  • Page 96: Status Register (Spsr)

    4/29/2020 Loongson 3A3000 / 3B3000 Processor User Manual Page 119 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 Rese Keep maste mode selection bit, this bit keeps 1 cp Yaol Clock polarity bit cpha Clock phase bit 1 is the opposite phase, and 0 is the same...
  • Page 97 SPI Flash Chip Select Control Register Chinese name: Register bit width: [7: 0] 0x05 Offset: 0x00 Reset value: Page 121 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 Bit field Bit field name Bit width access description 7: 4 csn pin output value...

  • Page 98: Io Controller Configuration

    11: 8T Page 122 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 11.5 IO controller configuration The configuration register is mainly used to configure the address window, arbiter and GPIO controller of the PCI controller. Table 11- 7 These registers are listed, and Table 11-8 gives a detailed description of the registers.
  • Page 99 Pre-fetch window mask high 32 bits PCI_H t0_Sel_L PCI window 0 controls the lower 32 bits Page 123 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 PCI window 0 controls the upper 32 bits PCI_H t0_Sel_H PCI_H t1_Sel_L...
  • Page 100 4/29/2020 Loongson 3A3000 / 3B3000 Processor User Manual Page 124 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 PCI_Mem_L Yao 2 Window map address high 6 bits 17:12 ans_l 耀 2 Read-write 0 31:18 Keep Read only 0...

  • Page 101: Chip Configuration Register List

    4/29/2020 Loongson 3A3000 / 3B3000 Processor User Manual 10: 32 cycles 11: 128 cycles 15: 8 level Read and write 8'h01 Equipment in the first level Mandatory priority device 23:16 ude_dev Read-write 0 The PCI device corresponding to the 1 bit can be obtained after the bus...
  • Page 102 CPU_WIN6_MASK 0x3ff00070 Mask of CPU window 6 CPU_WIN7_MASK 0x3ff00078 Mask of CPU window 7 Page 127 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 CPU_WIN0_MMAP 0x3ff00080 New base address of CPU window 0 0xf0 CPU_WIN1_MMAP 0x3ff00088 New base address of CPU window 1...
  • Page 103 Lock window mask 0 ([47: 0]: mask) Slock1_mask 0x3ff00248 Lock window mask 1 ([47: 0]: mask) Page 129 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 Slock2_mask 0x3ff00250 Lock window mask number 2 ([47: 0]: mask) Slock3_mask 0x3ff00258...
  • Page 104 4/29/2020 Loongson 3A3000 / 3B3000 Processor User Manual Page 130 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 MTX0_DST_ROW_STRIDE 0x3ff00628 MTX0_TRANS_CTRL 0x3ff00630 MTX1_SRC_START_ADDR 0x3ff00700 MTX1_DST_START_ADDR 0x3ff00708 MTX1_ORI_LENTH 0x3ff00710 MTX1_ORI_WIDTH 0x3ff00718 MTX1_SRC_ROW_STRIDE 0x3ff00720 MTX1_DST_ROW_STRIDE 0x3ff00728 MTX1_TRANS_CTRL 0x3ff00730 SCache0_perfctrl0 0x3ff00800...
  • Page 105 4/29/2020 Loongson 3A3000 / 3B3000 Processor User Manual SCache3_perfctrl2 0x3ff00B20 Page 132 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 SCache3_perfcnt2 0x3ff00B28 SCache3_perfctrl3 0x3ff00B30 SCache3_perfcnt3 0x3ff00B38 Core0_IPI_Status 0x3ff01000 IPI_Status register of processor core 0 Core0_IPI_Enalbe 0x3ff01004 IPI_Enalbe register of processor core 0...
  • Page 106 0x3ff0130c IPI_Clear register of processor core 3 Core3_MailBox0 0x3ff01320 IPI_MailBox0 register of processor core 3 Page 134 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 Core3_MailBox1 0x3ff01328 IPI_MailBox1 register of processor core 3 Core3_MailBox2 0x3ff01330 IPI_MailBox2 register of processor core 3...
  • Page 107 [59:58]: Hi_Sel3: Select the temperature sensor input source for high temperature interrupt 3 Page 136 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 Temperature sensor low temperature interrupt control register [7: 0]: Lo_gate0: low temperature threshold 0, below this temperature will generate an interrupt...
  • Page 108 4/29/2020 Loongson 3A3000 / 3B3000 Processor User Manual Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 Temperature sensor high-temperature down-frequency control register, four sets of setting priority from high to low [7: 0]: Scale_gate0: High temperature threshold 0, frequency will be reduced if this temperature is exceeded...
  • Page 109 4/29/2020 Loongson 3A3000 / 3B3000 Processor User Manual Page 139 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 CORE0 AXI interface AW trigger enable 0 is set, the highest bit is AW channel trigger enable [49: 0]: awmask...
  • Page 110 [63]: archannel_en: enable trigger condition CORE0_ARCOND1 0x3ff01830 [47: 0]: araddr CORE0_ARMASK1 0x3ff01838 Page 141 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 CORE0's AXI interface W trigger condition, similar to AW [15: 0]: wid [31:16]: wstrb [32]: wlast [33]: wvalid CORE0_WCOND0...
  • Page 111 0x3ff01890 CORE0_RMASK1 0x3ff01898 CORE0_RCOND2 0x3ff018a0 CORE0_RMASK2 0x3ff018a8 Page 143 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 TUD0 configuration register 0 [47: 0]: count_target TUD0_CONF0 0x3ff018e0 [55:48]: monitor_enable TUD0 configuration register 1 [2: 0]: DCDL_sel_signal [5: 3]: DCDL_sel_clock...
  • Page 112 4/29/2020 Loongson 3A3000 / 3B3000 Processor User Manual Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 CORE1 AXI interface AW trigger enable 0 is set, the highest bit is AW channel trigger enable The trigger condition is CORE1_AWMASK0 0x3ff01908 (AW_IN &...
  • Page 113 4/29/2020 Loongson 3A3000 / 3B3000 Processor User Manual Page 146 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 TUD1_RESULT 0x3ff019f0 TUD1 result register CORE2_AWCOND0 0x3ff01a00 CORE2 AXI interface AW trigger condition 0 setting CORE2's AXI interface AW trigger enable 0 setting, the highest bit is AW channel trigger enable...
  • Page 114 4/29/2020 Loongson 3A3000 / 3B3000 Processor User Manual Page 148 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 TUD0 configuration register 1 [2: 0]: DCDL_sel_signal [5: 3]: DCDL_sel_clock [9: 6]: signal_sel [13:10]: clok_sel [20:14]: reading_sel [21]: counter_clock_sel [22]: sticky...
  • Page 115 0x3ff01b90 CORE3_RMASK1 0x3ff01b98 CORE3_RCOND2 0x3ff01ba0 CORE3_RMASK2 0x3ff01ba8 Page 150 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 TUD3 configuration register 0 [47: 0]: count_target TUD3_CONF0 0x3ff01be0 [55:48]: monitor_enable TUD0 configuration register 1 [2: 0]: DCDL_sel_signal [5: 3]: DCDL_sel_clock...
  • Page 116 TUD5 configuration register 0 [47: 0]: count_target TUD5_CONF0 0x3ff01de0 [55:48]: monitor_enable Page 152 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 TUD5 configuration register 1 [2: 0]: DCDL_sel_signal [5: 3]: DCDL_sel_clock [8: 6]: signal_sel [11: 9]: clock_sel [18:12]: reading_sel...
  • Page 117 4/29/2020 Loongson 3A3000 / 3B3000 Processor User Manual Page 153 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 HT0_ARCOND0 0x3ff01e20 HT0's AXI interface AR trigger condition, similar to AW HT0_ARMASK0 0x3ff01e28 HT0_ARCOND1 0x3ff01e30 HT0_ARMASK1 0x3ff01e38 HT0_WCOND0 0x3ff01e40 HT0's AXI interface W trigger condition, similar to AW...
  • Page 118 HT1's AXI interface B trigger condition, similar to AW HT1_BMASK0 0x3ff01f78 HT1_RCOND0 0x3ff01f80 HT1's AXI interface R trigger condition, similar to AW HT1_RMASK0 0x3ff01f88 Page 155 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 HT1_RCOND1 0x3ff01f90 HT1_RMASK1 0x3ff01f98 HT1_RCOND2 0x3ff01fa0 HT1_RMASK2 0x3ff01fa8...
  • Page 119 First-level crossbar address window CORE1_WIN0_MASK 0x3ff02140 First-level crossbar address window CORE1_WIN1_MASK 0x3ff02148 First-level crossbar address window Page 157 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 CORE1_WIN2_MASK 0x3ff02150 First-level crossbar address window CORE1_WIN3_MASK 0x3ff02158 First-level crossbar address window CORE1_WIN4_MASK...
  • Page 120 First-level crossbar address window CORE2_WIN6_MMAP 0x3ff022b0 First-level crossbar address window CORE2_WIN7_MMAP 0x3ff022b8 First-level crossbar address window Page 159 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 CORE3_WIN0_BASE 0x3ff02300 First-level crossbar address window CORE3_WIN1_BASE 0x3ff02308 First-level crossbar address window CORE3_WIN2_BASE...
  • Page 121 4/29/2020 Loongson 3A3000 / 3B3000 Processor User Manual Page 160 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 CORE3_WIN3_MMAP 0x3ff02398 First-level crossbar address window CORE3_WIN4_MMAP 0x3ff023a0 First-level crossbar address window CORE3_WIN5_MMAP 0x3ff023a8 First-level crossbar address window CORE3_WIN6_MMAP 0x3ff023b0...
  • Page 122 First-level crossbar address window SOUTH_WIN7_BASE 0x3ff02538 First-level crossbar address window SOUTH_WIN0_MASK 0x3ff02540 First-level crossbar address window Page 162 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 SOUTH_WIN1_MASK 0x3ff02548 First-level crossbar address window SOUTH_WIN2_MASK 0x3ff02550 First-level crossbar address window SOUTH_WIN3_MASK...
  • Page 123 First-level crossbar address window WEST_WIN5_MMAP 0x3ff026a8 First-level crossbar address window WEST_WIN6_MMAP 0x3ff026b0 First-level crossbar address window Page 164 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 WEST_WIN7_MMAP 0x3ff026b8 First-level crossbar address window NORTH_WIN0_BASE 0x3ff02700 First-level crossbar address window NORTH_WIN1_BASE...

  • Page 124: Software And Hardware Design Guidelines

    Make some configuration changes to enable the original compatibility mode, or open some new features of Godson 3A3000 / 3B3000, This chapter focuses on the software and hardware settings of the Loongson 3A3000 / 3B3000 processor compared with Loongson 3A1000 / 2000 the difference.
  • Page 125 13.2 Frequency setting instructions In order to be basically compatible with the frequency configuration of Godson 3A1000, the hardware frequency configuration range of Godson 3A3000 / 3B3000 is relatively Narrow, in order to obtain a wider frequency range and better clock quality, it is mainly used in PMON in Godson 3A3000 / 3B3000 The software configuration method is the same as that of Godson 3B1500.
  • Page 126 Because from the processor core, memory controller, HT controller to all levels of crossbar switches have been upgraded to varying degrees, Therefore, compared with Loongson 3A1000, PMON needs to make some changes, mainly including the following necessary parts: 1. Remove the initialization operations of L1 Dcache, L1 Icache, Vcache, and L2 Cache after power-on (hardware completion);...
  • Page 127 Page 170 Godson 3A3000 / 3B3000 Processor User Manual • Volume 1 5. Use DI / EI to implement interrupt return. But it should be noted that the [31: 4] returned by the EI instruction is a random value, which is different from the MIPS...
  • Page 128 4/29/2020 Loongson 3A3000 / 3B3000 Processor User Manual...

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