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Loongson 3A2000 Manuals
Manuals and User Guides for Loongson 3A2000. We have
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Loongson 3A2000 manual available for free PDF download: User Manual
Loongson 3A2000 User Manual (126 pages)
volume One Multi-core processor architecture, register description and system software programming guide
Brand:
Loongson
| Category:
Computer Hardware
| Size: 0.5 MB
Table of Contents
Table of Contents
4
Loongson 3A2000 / 3B2000 Processor
7
1 Overview
12
Introduction to Loongson Series Processors
12
Introduction to Godson 3A2000 / 3B2000
13
Description of Loongson 3A2000 Commercial and Industrial Chips
15
2 System Configuration and Control
16
Chip Working Mode
16
Description of Control Pins
16
Cache Consistency
18
Address Routing Distribution and Configuration
19
Chip Configuration and Sampling Register
24
3 Gs464E Processor Core
27
4 Shared Cache (Scache)
29
5 Matrix Processing Accelerator
30
6 Interruption and Communication between Processor Cores
35
7 O Interrupt
35
8 Temperature Sensor
38
Real-Time Temperature Sampling
38
High and Low Temperature Interrupt Trigger
38
High Temperature Automatic Frequency Reduction Setting
39
9 DDR2 / 3 SDRAM Controller Configuration
40
DDR2 / 3 SDRAM Controller Function Overview
40
DDR2 / 3 SDRAM Read Operation Protocol
41
DDR2 / 3 SDRAM Write Operation Protocol
41
DDR2 / 3 SDRAM Parameter Configuration Format
42
Software Programming Guide
44
Control of Reset Pin
44
Leveling
46
Write Leveling
46
Gate Leveling
47
Initiate MRS Commands Separately
48
Self-Loop Test Mode Control
49
ECC Function Usage Control
49
10 Hypertransport Controller
50
Hypertransport Hardware Setup and Initialization
50
Hypertransport Protocol Support
52
Hypertransport Interrupt Support
53
Hypertransport Address Window
53
Hypertransport Space
54
Internal Window Configuration of Hypertransport Controller
54
Configuration Register
55
Bridge Control
56
Capability Registers
57
Receive Diagnostic Register
60
Interrupt Routing Mode Selection Register
60
Receive Buffer Initial Register
60
Receive Address Window Configuration Register
61
Interrupt Vector Register
63
Interrupt Enable Register
65
Interrupt Discovery & Configuration
68
POST Address Window Configuration Register
69
Prefetchable Address Window Configuration Register
70
UNCACHE Address Window Configuration Register
71
P2P Address Window Configuration Register
73
Command Send Buffer Size Register
74
Data Transmission Buffer Size Register
74
Send Buffer Debug Register
75
PHY Impedance Matching Control Register
75
Revision ID Register
76
Error Retry Control Register
76
Retry Count Register
76
Link Train Register
77
Training 0 Timeout Short Timer Register
77
Training 0 Time-Out Timer Register
78
Training 1 Count Register
78
Training 2 Count Register
78
Training 3 Count Register
78
Software Frequency Configuration Register
78
PHY Configuration Register
80
Link Initialization Debug Register
80
LDT Debug Register
81
Access Method of Hypertransport Bus Configuration Space
81
Hypertransport Bus Frequency Software Configuration Method
81
Hypertransport Multiprocessor Support
82
11 Low Speed IO Controller Configuration
84
PCI Controller
84
LPC Controller
88
UART Controller
89
Data Register (DAT)
89
Interrupt Enable Register (IER)
89
Interrupt Identification Register (IIR)
90
FIFO Control Register (FCR)
90
Line Control Register (LCR)
91
MODEM Control Register (MCR)
92
Line Status Register (LSR)
92
MODEM Status Register (MSR)
93
Frequency Division Latch
94
SPI Controller
94
Control Register (SPCR)
95
Status Register (SPSR)
95
Data Register (Txfifo)
95
Timing Control Register (SFC_TIMING)
97
IO Controller Configuration
97
12 Chip Configuration Register List
101
13 Software and Hardware Design Guidelines
123
Hardware Modification Guide
123
PMON Change Guide
124
Guidelines for Kernel Changes
125
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