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Loongson Godson 3A1000 User Manual

Volume one multi-core processor architecture, register description and system software programming guide
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4/29/2020
Godson 3A1000 Processor User Manual
Page 1
Godson 3A1000 Processor User Manual
volume One
Multi-core processor architecture, register description and system software programming guide
V1.15
Nian 09 Yue
2015
Loongson Zhongke Technology Co., Ltd.
Page 2
1

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Summary of Contents for Loongson Godson 3A1000

  • Page 1 4/29/2020 Godson 3A1000 Processor User Manual Page 1 Godson 3A1000 Processor User Manual volume One Multi-core processor architecture, register description and system software programming guide V1.15 Nian 09 Yue 2015 Loongson Zhongke Technology Co., Ltd. Page 2...
  • Page 2 Special presentations on common problems in the operating system development process. The second volume of the "Loongson 3A1000 Processor User Manual" introduces in detail the adoption of Loongson 3A1000 from the perspective of system software developers GS464 high-performance processor core.

  • Page 3: Godson 3A1000 Processor User Manual

    4/29/2020 Godson 3A1000 Processor User Manual Page 4 revise history Godson 3A1000 Processor User Manual Document name: Document update record --volume One V1.15 version number founder: R & D Center Creation Date: 2015-09-11 Update history Serial number Updated version number...
  • Page 4 Add the definition of HT register supported by LS3A1000E 13 2012-10-30 V1.12 Added matrix handling register supported by LS3A1000E 2014-04-02 V1.13 According to the chip naming rules, Loongson 3A processor was renamed Loongson 3A1000 Organizer 15 2014-07-24 V1.14 Add industrial-grade chip content 16 2015-09-11 V1.15 Revise the description of GPIO configuration register...

  • Page 5: Table Of Contents

    1.1 Introduction to Loongson series processors ..................2 1.2 Introduction to Godson 3A1000 ....................3 1.3 Description of Loongson 3A1000 Commercial and Industrial Chips ..............5 2 System Configuration and Control ....................6 2.1 Chip working mode ..................... 6 2.2 Description of control pins ........
  • Page 6 10.3.8 MODEM Status Register (MSR) ............110 10.3.9 Frequency Division Latch ................110 Page 8 Godson 3A1000 processor user manual directory 10.4 SPI controller ..................... 110 10.4.1 Control Register (SPCR) ................ 111 10.4.2 Status Register (SPSR) ................. 111 10.4.3 Data Register (TxFIFO) ..........
  • Page 7 14.3 Timing of configuring the address window of the first-level crossbar ..............136 14.4 Address window of secondary crossbar switch ................136 Page 9 Godson 3A1000 processor user manual directory 14.5 Special treatment for address window configuration ............... 137 14.6 HyperTransport Address Window ................138 14.6.1 External access window of processor core ...........
  • Page 8 Figure 8-2 DDR2 SDRAM read operation protocol ................... 32 Figure 8-3 DDR2 SDRAM write operation protocol ................... 32 Figure 9-1 HT protocol configuration access in Loongson No. 3 ..............96 Figure 9-2 Four-piece Loongson No. 3 interconnection structure ................97 Figure 9-3 Two-chip Loongson No.
  • Page 9 4/29/2020 Godson 3A1000 Processor User Manual Page 11 Godson 3A1000 processor user manual table entry Table directory Table 2-1 Control pin description ..................... 6 Table 2-2 Node-level system global address distribution ................8 Table 2-3 Address distribution in nodes ....................9 Table 2-4 Address distribution in nodes ..........
  • Page 10 Table 9-5 Address window distribution of HyperTransport interface of Loongson No. 3 processor ....... 80 Table 9-6 Address window provided in the HyperTransport interface of Loongson No. 3 processor ......81 Table 9-7 All software visible registers in this module ..............82 Table 10-1 PCIX Controller Configuration Header ..........

  • Page 11: First Part

    Core 2 superscalar processor and its IP series are mainly for desktop applications, and Godson 3 multi-core processor series is mainly for service Server and high-performance machine applications. According to the needs of the application, some of Loongson 2 can also face some high-end embedded Yes, some low-end Loongson 3 can also be used for some desktop applications.

  • Page 12: Introduction To Godson 3A1000

    Figure 1-1 Loongson No. 3 system structure The structure of Loongson No. 3 node is shown in Figure 1-2 below. Each node has two levels of AXI crossbars connected to the processor and two levels Cache, memory controller and IO controller. Among them, the first level AXI crossbar switch (called X1 Switch, referred to as X1) Connect the processor and secondary cache.
  • Page 13 The above two-level interconnect switches all use separate data channels for reading and writing. The width of the data channel is 128 bits. The processor core has the same frequency to provide high-speed on-chip data transmission. Based on Loongson No. 3 scalable interconnection architecture, 4 quad-core Loongson 3A1000 can be connected through HT port to form 4 chips 16-core SMP structure.

  • Page 14: Description Of Loongson 3A1000 Commercial And Industrial Chips

    GB 4937-1995 The Loongson 3A chip, like most semiconductor devices, has a failure rate that conforms to the bathtub curve model. Loongson 3A industrial grade chip In order to ensure longer-term, stable, and reliable operation, and to be able to adapt to more demanding environmental temperature requirements, the chip Reliability screening was conducted to eliminate early failure chips.

  • Page 15: Description Of Control Pins

    4/29/2020 Godson 3A1000 Processor User Manual ● Multi-chip interconnect mode. The system contains 2 pieces or 4 pieces Godson 3A1000, through the HT end of Godson 3A1000 It is a non-uniform memory access multiprocessor system (CC-NUMA). 2.2 Description of control pins The control pins of Loongson 3A1000 include DO_TEST, ICCC_EN, NODE_ID [1: 0], CLKSEL [15: 0], PCI_CONFIG.

  • Page 16: Cache Consistency

    2.3 Cache Loongson 3A1000 maintains the cache consistency between the processor and the I / O accessed through the HT port by hardware, but The hardware does not maintain the cache consistency of I / O devices connected to the system through PCI. During driver development, When PCI access devices perform DMA (Direct Memory Access) transmission, the software needs to perform Cache consistency maintain.
  • Page 17 0x1800_0000_0000, and so on. Unlike the mapping relationship of direction ports, Loongson 3A1000 can determine the second level according to the actual application access behavior Cache cross-addressing mode. The four Level 2 Cache modules in the node correspond to a total of 43 bits of address space, and each 2 The address space corresponding to the level module is determined according to one of the two selection bits of the address bit, and can be dynamically configured by software modify.

  • Page 18: Address Routing Distribution And Configuration

    Window hit formula: (IN_ADDR & MASK) == BASE Since Loongson 3 uses fixed routing by default, the configuration window is closed when the power is turned on. System software is required to enable and configure it. The address window conversion register is shown in the table below.
  • Page 19 0x3ff0_2400 EAST_WIN0_BASE 0x3ff0_2500 SOUTH_WIN0_BASE 0x3ff0_2408 EAST_WIN1_BASE 0x3ff0_2508 SOUTH_WIN1_BASE 0x3ff0_2410 EAST_WIN2_BASE 0x3ff0_2510 SOUTH_WIN2_BASE 0x3ff0_2418 EAST_WIN3_BASE 0x3ff0_2518 SOUTH_WIN3_BASE Page 24 Godson 3A1000 Processor User Manual Part 1 0x3ff0_2420 EAST_WIN4_BASE 0x3ff0_2520 SOUTH_WIN4_BASE 0x3ff0_2428 EAST_WIN5_BASE 0x3ff0_2528 SOUTH_WIN5_BASE 0x3ff0_2430 EAST_WIN6_BASE 0x3ff0_2530 SOUTH_WIN6_BASE 0x3ff0_2438 EAST_WIN7_BASE 0x3ff0_2538 SOUTH_WIN7_BASE...
  • Page 20 0x3ff0_2648 WEST_WIN1_MASK 0x3ff0_2748 NORTH_WIN1_MASK 0x3ff0_2650 WEST_WIN2_MASK 0x3ff0_2750 NORTH_WIN2_MASK 0x3ff0_2658 WEST_WIN3_MASK 0x3ff0_2758 NORTH_WIN3_MASK 0x3ff0_2660 WEST_WIN4_MASK 0x3ff0_2760 NORTH_WIN4_MASK Page 25 Godson 3A1000 Processor User Manual Part 1 0x3ff0_2668 WEST_WIN5_MASK 0x3ff0_2768 NORTH_WIN5_MASK 0x3ff0_2670 WEST_WIN6_MASK 0x3ff0_2770 NORTH_WIN6_MASK 0x3ff0_2678 WEST_WIN7_MASK 0x3ff0_2778 NORTH_WIN7_MASK 0x3ff0_2680 WEST_WIN0_MMAP 0x3ff0_2780 NORTH_WIN0_MMAP...
  • Page 21 Will be inconsistent with the address of the first-level cache of the processor, resulting in incorrect maintenance of Cache consistency. Page 26 Godson 3A1000 Processor User Manual Part 1 Window hit formula: (IN_ADDR & MASK) == BASE New address conversion formula: OUT_ADDR = (IN_ADDR & ~ MASK) | {MMAP [63:10], 10'h0} The address window conversion register is as follows.
  • Page 22 4/29/2020 Godson 3A1000 Processor User Manual Page 27 Godson 3A1000 Processor User Manual Part 1 3ff0 0100 PCI_WIN0_BASE PCI window 0 base address 0x8000_0000 3ff0 0108 PCI_WIN1_BASE PCI window 1 base address 0x0 3ff0 0110 PCI_WIN2_BASE PCI window 2 base address 0x0...

  • Page 23: Chip Configuration And Sampling Register

    1: open 0: disabled Whether to enable DDR controller 0 16 Mc0_en 1'b1 1: open Page 29 Godson 3A1000 Processor User Manual Part 1 0: disabled Whether to enable DDR controller 1 17 Mc1_en 1'b1 1: open 0: disabled Software reset DDR controller 0...
  • Page 24 2v5pad control 31:16 Pad3v3_ctrl 16'h780 3v3pad control Page 30 Godson 3A1000 Processor User Manual Part 1 Onboard frequency setting 47:32 Sys_clksel Indicates whether the processor core is unavailable, each bit Do not correspond to processor core 3-processor core 0 51:48 Bad_ip_core...

  • Page 25: Gs464 Processor Core

    Applications and desktop applications can also be used as basic processor cores to form on-chip multi-core systems for server and high-performance applications use. Multiple GS464 cores in Loongson 3A1000 and the secondary cache module form one through the AXI interconnection network Multi-core structure of distributed shared secondary cache.

  • Page 26: Secondary Cache

    4/29/2020 Godson 3A1000 Processor User Manual Page 32 Godson 3A1000 Processor User Manual Part 1 GS464 Commit Bus Reorder Queue Branch Bus Write back Bus Map Bus ALU1 ecode B PC + 16 Integer DCACHE Queue ALU2 egister M Pre-D...
  • Page 27 Page 34 Godson 3A1000 Processor User Manual Part 1 If it is hit and locked in the secondary cache, the DMA write will be directly written to the secondary cache instead of memory. Table 4-1 Secondary Cache Lock Window Register Configuration...

  • Page 28: Matrix Processing Accelerator

    5 Matrix processing accelerator There are two matrix processing accelerators independent of the processor core built into Loongson 3A1000, the basic function of which is through software The configuration of the matrix can be used to transpose or move the matrix stored in the memory from the source matrix to the target matrix (The previous version of LS3A1000E only supports the transpose function).
  • Page 29 0x3ff00600 Src_start_addr of transpose module 0 0x3ff00608 Dst_start_addr of transpose module 0 twenty three Page 36 Godson 3A1000 Processor User Manual Part 1 0x3ff00610 Row 0 transpose module 0x3ff00618 Col of transpose module 0 0x3ff00620 Length of transposed module 0...
  • Page 30 4/29/2020 Godson 3A1000 Processor User Manual twenty four Page 37 Godson 3A1000 Processor User Manual Part 1 Table 5-4 Explanations of the trans_status registers Field Explanation Source matrix read The target matrix is written Page 38 Godson 3A1000 Processor User Manual Part 1...
  • Page 31 Godson 3A1000 Processor User Manual Loongson 3A1000 implements 8 inter-core interrupt registers (IPI) for each processor core to support multi-core BIOS boot Interrupt and communication between the processor cores when the mobile and operating system are running, the description and addresses are shown in Table 6-1 to Table 6-5.

  • Page 32: O Interrupt

    7 I / O interrupt Loongson 3A1000 chip supports up to 32 interrupt sources, which are managed in a unified manner, as shown in Figure 7-1 below, An IO interrupt source can be configured as enabled, triggered, and routed to the processor core interrupt pin.
  • Page 33 0x3ff01458 Four processor cores are integrated in Loongson 3A1000. The above 32-bit interrupt sources can be selected through software configuration. The target processor core is expected to be interrupted. Further, the interrupt source can be selected to route to any of the processor core interrupts Meaning one, that is, IP2 to IP5 corresponding to CP0_Status.
  • Page 34 Godson 3A1000 Processor User Manual 3: 0 Routed processor core vector number Routed processor core interrupt pin vector number 7: 4 Page 42 Godson 3A1000 Processor User Manual Part 1 Table 7-4 Interrupt Routing Register Address name Address offset description name...

  • Page 35: Ddr2 / 3 Sdram Controller Configuration

    8 DDR2 / 3 SDRAM controller configuration The design of the integrated memory controller inside Loongson No. 3 processor complies with the industry standard of DDR2 / 3 SDRAM (JESD79-2 And JESD79-3). In the Godson 3 processor, all memory read / write operations are implemented in compliance with JESD79-2B and The provisions of JESD79-3.

  • Page 36: Ddr2 / 3 Sdram Write Operation Protocol

    The memory controller will automatically initiate initialization commands to the memory. In the design of Loongson 3 processor, the configuration of DDR2 / 3 SDRAM needs to be Before using memory, configure the memory type. The specific configuration operation is to physical address 0x0000 0000 0FF0 0000 The corresponding 180 64-bit registers write the corresponding configuration parameters.
  • Page 37 The controller will use the number and data specified by the xor_check_bits parameter Page 46 Godson 3A1000 Processor User Manual Part 1 Write XOR to memory (write only) Whether to allow the controller to open the fast write function. Open Quick Write After the function is enabled, the controller sends the memory mode after receiving all the written data.
  • Page 38 0x0-0x1 When the command queue reordering logic is enabled, when the high priority command Page 47 Godson 3A1000 Processor User Manual Part 1 When arriving, whether to exchange the command being executed with the new command Whether to initialize the memory. All parameters are required...
  • Page 39 Configure according to specific memory particles and operating frequency. TCKE 2: 0 0x0-0x7 defines the minimum pulse width of CKE signal Page 49 Godson 3A1000 Processor User Manual Part 1 CONF_CTL_07 [63: 0] Offset: 0x70 DDR2 667: 0x0f0e0200000f0a0a MAX_ROW_REG 59:56...
  • Page 40 Do not correspond to CS0-CS3 Page 50 Godson 3A1000 Processor User Manual Part 1 Define the CS2 ODT terminal when CS2 has a read command The terminal resistance is valid, the specific configuration should refer to the corresponding memory chip...
  • Page 41 0x0-0x3f defines the command queue reordering logic when using the aging algorithm Page 51 Godson 3A1000 Processor User Manual Part 1 The initial aging value of the command Define the active commands between the same bank of the memory module...
  • Page 42 15: 0 0x0000 0x0-0xffff Configuration. Page 52 Godson 3A1000 Processor User Manual Part 1 CONF_CTL_20 [63: 0] Offset: 0x140 DDR2 667: 0x0000204002000030 When the fwc parameter is set, the check bit of the next write operation will be XOR_CHECK_BITS 63:48...
  • Page 43 4/29/2020 Godson 3A1000 Processor User Manual Godson 3A1000 Processor User Manual Part 1 CONF_CTL_26 [63: 0] Offset: 0x1a0 DDR2 667: 0x0000000000000000 0x0-0x1fffffff Record data information when 2bit ECC error occurs (read only) ECC_U_DATA [63:32] 63:32 0x0-0x1fffffff Record data information when 2bit ECC error occurs (read only)
  • Page 44 360. In Godson 3, this value is generally 1/4, Ie 8'h20 Page 55 Godson 3A1000 Processor User Manual Part 1 7: 0: Control the accuracy of the internal DLL. In, this value is generally 8'h80 The third data group (DQ31-DQ24) DLL control signal...
  • Page 45 In the number, this value is generally 1/4, which is 8'h20 7: 0: Control the accuracy of the internal DLL. In Godson 3, this Page 56 Godson 3A1000 Processor User Manual Part 1 The value is generally 8'h80 7th data group (DQ63-DQ56) DLL control signal...
  • Page 46 0x0000 0x0-0xffffffff 15: 8: When the read data returns, the phase of DQSn is delayed. 5: 0: Page 57 Godson 3A1000 Processor User Manual Part 1 DLL test control signal, normally 8'h0. 6th data group DLL control signal DLL_CTRL_REG_1_6 31: 0 0x0000 0x0-0xffffffff 15: 8: When the read data returns, the phase of DQSn is delayed.
  • Page 47 Godson 3A1000 Processor User Manual Part 1 Disable Disable 1: MODEZI1v8 corresponding to the pin For Loongson 3, it should be set to 0. 0: DDR1v8 corresponding to the pin 0: Corresponding to the 1.8v mode of DDRII 1: 1.5v mode corresponding to DDRIII...
  • Page 48 27: Use read FIFO effective signal to automatically control read data return Sampling (1), or use fixed time sampling in 26:24 (0) Page 60 Godson 3A1000 Processor User Manual Part 1 26:24: Reading data returns to the timing of sampling completion, from the internal clock The sampling delay of the domain.
  • Page 49 15:12: Effective start time for writing DQS, for DDR3 It should be opened one cycle earlier than DDR2 to provide particle requirements Page 61 Godson 3A1000 Processor User Manual Part 1 Preamble DQS 11: 8: The effective end time for writing DQS...
  • Page 50 The sampling delay of the domain. 21: In Read Leveling mode, sample the data bus Page 62 Godson 3A1000 Processor User Manual Part 1 Level 20: The level of the effective data control signal, which is 0 in Godson 3...
  • Page 51 4/29/2020 Godson 3A1000 Processor User Manual Page 63 Godson 3A1000 Processor User Manual Part 1 CONF_CTL_49 [63: 0] Offset: 0x310 DDR2 667: 0xf3002947f3002947 Data group 8 delay control. 28: Whether to use deburring circuit for reading DQS, refer to gate...
  • Page 52 27:24: Timing control of terminal resistance off 23: Effective level control of termination resistance Page 65 Godson 3A1000 Processor User Manual Part 1 Is 1 22: Enable signal of the terminating resistor, when it is 1, the dynamic square is used The control of the termination resistance is enabled;...
  • Page 53 31:28: Timing control of terminal resistance opening, read command sent from The calculation starts after the last 4 beats, each value represents a half cycle Page 66 Godson 3A1000 Processor User Manual Part 1 27:24: Timing control of terminal resistance off 23: Effective level control of termination resistance...
  • Page 54 0x00000 0x0-0xffffffff Will only be enabled when Page 67 Godson 3A1000 Processor User Manual Part 1 31:28: Timing control of terminal resistance opening, read command sent from The calculation starts after the last 4 beats, each value represents a half cycle...
  • Page 55 4/29/2020 Godson 3A1000 Processor User Manual Page 68 Godson 3A1000 Processor User Manual Part 1 Terminal resistance control of PAD in the 6th data group, initiate read operation Will only be enabled when 31:28: Timing control of terminal resistance opening, read command sent from...
  • Page 56 0x0-0x1 Enable pre-sampling check when reading strobe sampling training RDLVL_GATE_PREA Page 70 Godson 3A1000 Processor User Manual Part 1 MBLE_CHECK_EN Read strobe sampling training when Read Leveling is enabled, in the initial After the completion of the conversion, it will send a command to the particle to read the DQS sampling...
  • Page 57 0x0-0x3 Whether internal port 1 can be executed out of order, invalid for Godson No. 3 AXI1_PORT_ORDERI 57:56 Page 71 Godson 3A1000 Processor User Manual Part 1 AXI0_PORT_ORDERI 49:48 0x0-0x3 Whether internal port 0 can be executed out of order WRLVL_REQ 0x0-0x1 User request to start Write Leveling training function.
  • Page 58 Relative priority of commands of internal port 0 priority 0 AXI0_PRIORITY0_RE 43:40 0x0-0xf LATIVE_PRIORITY Page 72 Godson 3A1000 Processor User Manual Part 1 ADDRESS_MIRRORI 35:32 0x0-0xf indicates which chip select supports Address mirroring TDFI_DRAM_CLK_DI 26:24 0x0-0x7 Delay setting from internal clock off to external clock off...
  • Page 59 4/29/2020 Godson 3A1000 Processor User Manual Page 73 Godson 3A1000 Processor User Manual Part 1 Define the external memory type of the controller DRAM_CLASS 19:16 0x0-0xf 110: DDR3 100: DDR2 BURST_ON_FLY_BIT 11: 8 0x0-0xf burst-on-fly bit in the mode configuration issued to DRAM...
  • Page 60 CONF_CTL_128 [63: 0] Offset: 0x800 DDR2 667: 0x0000000000000000 OBSOLETE CONF_CTL_129 [63: 0] Offset: 0x810 DDR2 667: 0x0000000000000000 OBSOLETE Page 75 Godson 3A1000 Processor User Manual Part 1 CONF_CTL_130 [63: 0] Offset: 0x820 DDR2 667: 0x0420000c20400000 TDFI_WRLVL_RESPL 63:56 0x00 0x0-0xff Write Leveling Strobe to valid number of cycles...
  • Page 61 LOWPOWER_EXTER Counts idle cycles to self-refresh with memory 47:32 0x0000 0x0-0xffff NAL_CNT clock gating. Enable various narrow accesses on internal port 2 for Loongson 3 AXI2_EN_SIZE_LT_W 31:16 0x0000 0x0-0xffff invalid IDTH_INSTR Enable various narrow accesses on internal port 1, for Godson 3...
  • Page 62 23:16: Delay of CLK2 and CLK3 on the output clock DLL Page 77 Godson 3A1000 Processor User Manual Part 1 15: 8: Delay of CLK0 and CLK1 on the output clock DLL 7: 0: Accuracy value on output clock DLL...
  • Page 63 4/29/2020 Godson 3A1000 Processor User Manual CONF_CTL_149 [63: 0] Offset: 0x950 DDR2 667: 0x0000000000000a03 Page 78 Godson 3A1000 Processor User Manual Part 1 Interrupt mask [18] = OR of all interrupt bits; [17] = User initiated DLL synchronization end flag;...
  • Page 64 [11] = An error in reading the sample training results; [10] = An error reading the training results; Page 80 Godson 3A1000 Processor User Manual Part 1 [9] = ODT is enabled, and CAS Latency is 3; [8] = DRAM initialization completed;...
  • Page 65 Number of cycles TBST_INT_INTERVAL 42:40 0x0-0x7 DRAM burst interrupt interval period Page 81 Godson 3A1000 Processor User Manual Part 1 When the additional delay from the read command to the write command of the same chip select R2W_SAMECS_DLY 34:32 0x0-0x7...
  • Page 66 The number of clock cycles required for a normal ZQCL command, it should be equal to ZQCL 43:32 0x0-0xfff Half of ZQINIT Page 82 Godson 3A1000 Processor User Manual Part 1 TDFI_WRLVL_WW 25:16 0x0-0x3ff Minimum number of clock cycles between two consecutive leveling commands TDFI_RDLVL_RR 9: 0...
  • Page 67 0x0-0xffff In the third data group, from the first 1 to the Read Leveling RDLVL_BEGIN_DELA 63:48 Page 83 Godson 3A1000 Processor User Manual Part 1 0 number of delay units In the second data set, from the first 1 to the Read Leveling...
  • Page 68 RDLVL_GATE_DELAY 31:16 0x0-0xffff Number of late units Page 85 Godson 3A1000 Processor User Manual Part 1 In the first data group, the delay from the sampling timing to the rising edge of the strobe signal RDLVL_GATE_DELAY 15: 0 0x0-0xffff Number of late units...
  • Page 69 CONF_CTL_172 [63: 0] Offset: 0xac0 DDR2 667: 0x0000000000000000 0x0-0xffff When the Hardware read leveling module is enabled, equal to RDLVL_MIDPOINT_D 63:48 Page 86 Godson 3A1000 Processor User Manual Part 1 ELAY_8 of rdlvl_begin_delay_8 and rdlvl_end_delay_8 Interval, otherwise, equal to rdlvl_delay_8 (read only)
  • Page 70 (Should be set to 0) TERVAL 0x0-0xffff 8th data set, offset to the midpoint of Read Leveling RDLVL_OFFSET_DEL 15: 0 Page 87 Godson 3A1000 Processor User Manual Part 1 AY_8 CONF_CTL_176 [63: 0] Offset: 0xb00 DDR2 667: 0x0000000000000000 WRLVL_DELAY_5 63:48...

  • Page 71: Hypertransport Controller

    4/29/2020 Godson 3A1000 Processor User Manual Page 88 Godson 3A1000 Processor User Manual Part 1 9 HyperTransport controller In Godson 3, the HyperTransport bus is used to connect external devices and interconnect multiple chips. When used for peripheral connection, The user program can freely choose whether to support IO Cache consistency (set by the address window Uncache window, see x.4.2 Section).
  • Page 72 HT0_Rx_CLKp [1: 0] CLK [1: 0] HyperTransport bus CLK signal Page 90 Godson 3A1000 Processor User Manual Part 1 HT0_Rx_CLKn [1: 0] When HT0_8x2 is 1, CLK [1] is controlled by HT0_Hi HT0_Tx_CLKp [1: 0] CLK [0] is controlled by HT0_Lo...

  • Page 73: Hypertransport Protocol Support

    1 – Doubleword bit 1: Don't Care bit 1: Don't Care bit 0: Don't Care bit 0: must be 1 Page 91 Godson 3A1000 Processor User Manual Part 1 Read operation returns 110000 R RdResponse Write operation returns 110011 R...

  • Page 74: Hypertransport Interrupt Support

    The distribution of the specific address windows between is described in the following table. The address window of HyperTransport interface protocol of Godson 3 processor is as follows: Table 9-5 Address window distribution of HyperTransport interface of Loongson 3 processor Base address...
  • Page 75 Godson 3 processor HyperTransport interface provides a variety of rich address windows for users to use, including Page 93 Godson 3A1000 Processor User Manual Part 1 As follows: Table 9-6 Address window provided in HyperTransport interface of Loongson 3 processor Address window Window number accept bus effect...
  • Page 76 4/29/2020 Godson 3A1000 Processor User Manual Godson 3A1000 Processor User Manual Part 1 Table 9-7 All software visible registers in this module Offset address name description 0x30 0x34 0x38 0x3c Bridge Control Bus Reset Control 0x40 Command, Capabilities Pointer, Capability ID...
  • Page 77 In R / W HOST mode: can be used to record the number of IDs used In SLAVE mode: record your own Unit ID No dual HOST mode Double Ended Page 96 Godson 3A1000 Processor User Manual Part 1 Warm Reset Bridge Control uses warm reset in reset Next Cap register offset address 15: 8...
  • Page 78 High 8-bit PHY shutdown control 1: Turn off the upper 8-bit HT PHY 0: enable high 8-bit HT PHY Page 97 Godson 3A1000 Processor User Manual Part 1 Offset: 0x48 Reset value: 0x80250023 Name: Revision ID, Link Freq, Link Error, Link Freq Cap...
  • Page 79 The correct way is to set 0 first and then set 0: 0-> 1 In addition, direct read and write requests to the bus can also be automatically Wake up bus Page 98 Godson 3A1000 Processor User Manual Part 1 Bit field Bit field name Bit width reset value Visit description...
  • Page 80 4/29/2020 Godson 3A1000 Processor User Manual Page 99 Godson 3A1000 Processor User Manual Part 1 9.5.5 Interrupt routing mode selection register (LS3A1000E and above) Offset: 0x58 Reset value: 0x00000000 Name: Interrupt routing mode selection register Bit field Bit field name...
  • Page 81 R / W HT bus receive address window 2, the translated address [53:24], trans [53:24] For LS3A1000D and below, [29:23] is fixed at Page 101 Godson 3A1000 Processor User Manual Part 1 Offset: 0x74 Reset value: 0x00000000 Name: HT bus receive address window 2 base address (external access)
  • Page 82 The following description of the interrupt vector corresponds to ht_int_stripe_1, and the other two methods can be obtained from the above description. For LS3A1000D and below, only ht_int_stripe_1 can be used. Page 102 Godson 3A1000 Processor User Manual Part 1 Offset: 0x80 Reset value: 0x00000000...
  • Page 83 Corresponding to interrupt line 2 / HT HI Corresponding to interrupt line 6 Offset: 0x98 Reset value: 0x00000000 Name: HT Bus Interrupt Vector Register [223: 192] Page 103 Godson 3A1000 Processor User Manual Part 1 Bit field Bit field name Bit width reset value Visit description 31: 0...
  • Page 84 4/29/2020 Godson 3A1000 Processor User Manual Page 104 Godson 3A1000 Processor User Manual Part 1 Name: HT Bus Interrupt Enable Register [159: 128] Bit field Bit field name Bit width reset value Visit description 31: 0 Interrupt_mask R / W HT bus interrupt enable register [159: 128],...
  • Page 85 Name: HT bus POST address window 1 enable (internal access) Bit field Bit field name Bit width reset value Visit description Page 106 Godson 3A1000 Processor User Manual Part 1 Bit field Bit field name Bit width reset value Visit description ht_post1_en...
  • Page 86 Name: HT bus prefetch address window 1 enabled (internal access) Bit field Bit field name Bit width reset value Visit description Page 107 Godson 3A1000 Processor User Manual Part 1 Bit field Bit field name Bit width reset value Visit description ht_prefetch1_en...
  • Page 87 Off, the method of access may be slightly different. As shown in Table 9-5, the configuration access space is located at the address 0xFD_FE00_0000 to 0xFD_FFFF_FFFFh. For configuration access in the PCI protocol, in Loongson No. 3, such as The next realization.
  • Page 88 Loongson 3 interconnection routing Loongson No. 3 interconnection routing adopts simple XY routing method. That is, when routing, X then Y, taking four chips as an example, ID The numbers are 00, 01, 10, and 11, respectively. If a request is made from 11 to 00, it is a route from 11 to 00, first go to X Direction, from 11 to 10, then Y direction, from 10 to 00.
  • Page 89 10.1 PCI / PCI-X controller The PCI / PCI-X controller of Loongson 3 can be used as the main bridge to control the entire system, or it can be used as an ordinary PCI / PCI-X devices work on the PCI / PCI-X bus. Its implementation conforms to PCI-X 1.0b and PCI 2.3 specifications. Dragon The PCI / PCI-X controller of Core 3 also has a built-in PCI / PCI-X arbiter.
  • Page 90 Godson 3A1000 Processor User Manual Part 1 The PCIX controller of Loongson 3A1000 supports three 64-bit windows, composed of {BAR1, BAR0}, {BAR3, BAR2}, {BAR5, BAR4} The base address of three pairs of register configuration windows 0, 1, 2. The size, enable, and other details of the The three corresponding registers PCI_Hit0_Sel, PCI_Hit1_Sel, PCI_Hit2_Sel control, please refer to Table 2 for specific bit fields.
  • Page 91 12: 5 delay visit 13: 6 delay visit 14: 7 delay visit Page 113 Godson 3A1000 Processor User Manual Part 1 15: 8 delay visit Prefetchable boundary configuration (in units of 16 bytes) FFF: 64KB to 16byte Read and write 000h...
  • Page 92 4/29/2020 Godson 3A1000 Processor User Manual Page 114 Godson 3A1000 Processor User Manual Part 1 10: 0 Reserved REG_50 Vector of unprocessed request number of master Read and write 0 31: 0 mas_pending_seq The corresponding bit can be cleared by writing 1...
  • Page 93 Bus docking refers to whether or not to select one to give an enable signal when no device requests to use the bus. For already As far as allowed devices are concerned, directly initiating bus operations can improve efficiency. Loongson 2F's PCI arbiter provides two kinds of stop By mode: the last master device and the default master device.
  • Page 94 REG3 [17: 0] LPC_INT_CLEAR LPC SIRQ interrupt clear Page 117 Godson 3A1000 Processor User Manual Part 1 10.3 UART controller The UART controller has the following features ● Full duplex asynchronous data receiving / sending ● Programmable data format ●...
  • Page 95 Receive valid data interrupt enable '0' – close '1' – open IRxE Interrupt Identification Register ( IIR ) 10.3.3 Chinese name: Interrupt source register Page 118 Godson 3A1000 Processor User Manual Part 1 Register bit width: [7: 0] Offset: 0x02 Reset value: 0xc1 Bit field Bit field name...
  • Page 96 4/29/2020 Godson 3A1000 Processor User Manual Page 119 Godson 3A1000 Processor User Manual Part 1 Keep 5: 3 Reserved Txset '1' Clear the content of transmit FIFO, reset its logic Rxset '1' Clear the content of the receive FIFO, reset its logic...
  • Page 97 Line Status Register ( LSR ) 10.3.7 Chinese name: Line Status Register Register bit width: [7: 0] Offset: 0x05 Reset value: 0x00 Page 121 Godson 3A1000 Processor User Manual Part 1 Bit field Bit field name Bit width access description Error indication bit ERROR '1'-at least parity error, framing error or interruption The broken one.
  • Page 98 '1' – There is data in the FIFO Page 122 Godson 3A1000 Processor User Manual Part 1 When reading this register, LSR [4: 1] and LSR [7] are cleared, and LSR [6: 5] when writing data to the transmit FIFO Cleared, LSR [0] judges the receive FIFO.
  • Page 99 7: 0 10.4 SPI controller The SPI controller has the following features: Page 123 Godson 3A1000 Processor User Manual Part 1 ● Full duplex synchronous serial data transmission ● Supports up to 4 variable-length byte transmission ● Main mode support ●...
  • Page 100 4/29/2020 Godson 3A1000 Processor User Manual Clear Page 124 Godson 3A1000 Processor User Manual Part 1 Keep 5: 4 Reserved Write register full flag 1 means full wffull Write register empty flag 1 means empty wfempty Read register full flag 1 means full...
  • Page 101 PCI window 0 controls the lower 32 bits PCI_Hit0_Sel_L PCI window 0 controls the upper 32 bits PCI_Hit0_Sel_H Page 126 Godson 3A1000 Processor User Manual Part 1 PCI Window 1 controls the lower 32 bits PCI_Hit1_Sel_L PCI_Hit1_Sel_H PCI Window 1 controls the upper 32 bits...
  • Page 102 PCI_Mem_Lo2 window map address high 6 bits Read only 0 31:18 Reserved CR14: PCIX_Bridge_Cfg Page 127 Godson 3A1000 Processor User Manual Part 1 Read and write 6'h18 Threshold for sending data to DDR2 in PCIX mode 5: 0 pcix_rgate Read-write 0...
  • Page 103 Read-write 0 Mandatory priority device 23:16 rude_dev Page 128 Godson 3A1000 Processor User Manual Part 1 The PCI device corresponding to the 1 bit can be obtained after the bus To occupy the bus with continuous requests Read only 0...
  • Page 104 Temperature sensor 0 temperature, used to monitor the secondary cache attached 102: 96 Thsens0_out Near temperature, accuracy is +/- 6 degrees Celsius Page 129 Godson 3A1000 Processor User Manual Part 1 Read only Temperature sensor 0 temperature overflow (over 128 degrees) Thsens0_overflow...
  • Page 105 11.1 Interrupted process The process of Loongson 3A1000 handling interrupts, from the external interrupt request to the kernel's handling of interrupts, the process is the same of. The following figure shows the flow chart of the interrupt processing of 3A-690e board.
  • Page 106 11.2 Interrupt routing and interrupt enable Loongson 3A1000 chip supports up to 32 interrupt sources, managed in a unified manner, as shown in the following figure, any one An IO interrupt source can be configured to enable, trigger, and route the interrupt pin of the target processor core.
  • Page 107 11.2.1 Four processor cores are integrated in Loongson 3A1000. The above 32-bit interrupt sources can be selected through software configuration. The target processor core is expected to be interrupted. Further, the interrupt source can be optionally routed to the processor core interrupt INT0 to INT3 Any one, namely IP2 to IP5 corresponding to CP0_Status.
  • Page 108 * (volatile unsigned char *) 0x900000003ff0141c = 0x21; * (volatile unsigned char *) 0x900000003ff0141d = 0x21; Page 134 Godson 3A1000 Processor User Manual Part 2 * (volatile unsigned char *) 0x900000003ff0141e = 0x21; * (volatile unsigned char *) 0x900000003ff0141f = 0x21;...
  • Page 109 4/29/2020 Godson 3A1000 Processor User Manual Godson 3A1000 Processor User Manual Part 2 Independent enable, such as LPC interrupt controller, HT interrupt controller, specific register configuration can check the register manual. below Lists some interrupt controllers that may need to be enabled: / * Enable the IO interrupt controller, LPC (10) and HT (16 ~ 31) * / t = * (volatile unsigned int *) 0x900000003ff01428;...
  • Page 110 4/29/2020 Godson 3A1000 Processor User Manual Page 137 Godson 3A1000 Processor User Manual Part 2 12 Serial port configuration and use 12.1 Optional serial port As a communication interface, serial port is mainly used for system debugging. The working principle is to configure the serial port baud Registers related to rate, data bits, stop bits, and parity bits enable the serial port to send and receive bytes bit by bit.
  • Page 111 // The data bits are 8 bits t1,0 t1,1 (a0) // Do not use interrupt Page 138 Godson 3A1000 Processor User Manual Part 2 t1,71 t1,2 (a0) // Set FIFO control register END (initserial) GS3_UART_BASE is also defined in the start.S file, which is 0xbfe001e0.
  • Page 112 The serial port of the CPU or the serial port of the LPC is used. The distribution of interrupts is also slightly different. The section on serial interrupts in irq.c Points are as follows: Page 139 Godson 3A1000 Processor User Manual Part 2 ..} else if (pending & CAUSEF_IP2) {// For LPC #ifdef CONFIG_CPU_UART do_IRQ (58);...
  • Page 113 Using the debugging memory space controlled by the debugging host, the debugging service can complete almost any conceivable function, because The code for the debugging service program itself can be provided by the debugging host (currently not available in the samples of Godson 3A1000 and 2G Get instructions from dmseg, but can execute memory access instructions).
  • Page 114 = 3, address = 0000000000000017, value = 0000000000000000 | t2 Page 142 Godson 3A1000 Processor User Manual Part 2 pracc write, size = 3, address = 000000000000001f, value = fffffffff80e1060 | t3 pracc write, size = 3, address = 0000000000000027, value = ffffffff8000b899 | t4...
  • Page 115 = 3, address = 0000000000000107, value = 00000000000001fc Page 143 Godson 3A1000 Processor User Manual Part 2 pracc write, size = 3, address = 0000000000000107, value = 0000000000000001 pracc write, size = 3, address = 0000000000000107, value = ffffffffbfc00480...
  • Page 116 0x100 (t0) // debug ... dextu (_t2, _t1, 2-1, 48-32) Page 144 Godson 3A1000 Processor User Manual Part 2 sd t2, 0x100 (t0) // debug ... dextu (_t3, _t1, 9-1, 50-32) sd t3, 0x100 (t0) // debug ...
  • Page 117 14 Address window configuration conversion Loongson 3A1000 adopts two-stage cross switch structure, two-stage cross switch window can be configured separately for controlling The address is sent to a specific receiver for processing. In addition, the HyperTransport controller is also internal to the chip and external to the chip.
  • Page 118 Main port 0: processor core 0 Main port 1: processor core 1 Main port 2: processor core 2 Page 147 Godson 3A1000 Processor User Manual Part 2 Main port 3: processor core 3 Main port 6: HyperTransport 0 Main port 7: HyperTransport 1...
  • Page 119 0x0BFF_FFFF_FFFF Which two are mapped to different four secondary Cache. See section 2.4 of the user manual for details. Page 148 Godson 3A1000 Processor User Manual Part 2 E.g, When scid_sel = 0, 0x000: route to secondary cache 0 0x020: Route to secondary cache 1...
  • Page 120 14.5 Special treatment for address window configuration Since Loongson 3A1000 processor cores will have some guessed access to the outside, these guessed accesses may fall to Address space. However, not all devices are allowed to be accessed by guessing, especially for PCI devices, a guess The measured read access is likely to cause the destruction of a "read clear"...
  • Page 121 External access window of processor core 14.6.1 Loongson 3A1000 chip has 4 HyperTransport controllers, namely HT0_LO, HT0_HI, HT1_LO, HT1_HI, where HT0_LO and HT0_HI share a physical interface, HT1_LO and HT1_HI Sharing a physical interface, when the chip pin HTx_8x2 is set low, only HTx_LO is visible to the user, and HTx_HI 'S address space is invalid.
  • Page 122 A set of windows is provided, namely the “Receive Address Window” in Section 9.5.4 of the user manual, only the DMA locations that fall in this set of windows Page 152 Godson 3A1000 Processor User Manual Part 2 The address will be truly operated on the memory space in the chip, otherwise it will make an error response to the peripheral that initiated the access.
  • Page 123 The following describes the configuration of the two-level crossbar in PMON. In the following example, the HT device Use HT1 interface connection, HT0 interface is not used. Page 153 Godson 3A1000 Processor User Manual Part 2 14.7.1 Example of a level 1 crossbar 1...
  • Page 124 These addresses will not appear actively during normal program execution, but due to the speculative execution of the processor core, any Address access may occur. If the correct response is not obtained, the processor may crash. Godson 3A1000 The HT controller can correctly identify and handle such access. Therefore, all these potential guess visits need to be routed to HT controller.
  • Page 125 Godson 3A1000 Processor User Manual Page 155 Godson 3A1000 Processor User Manual Part 2 Window 3 routes all the addresses of 0x0000_0E00_0000_0000 to the HT1 controller, which is the default A routing method, this configuration is done because in windows 4-7, all addresses are routed to four different In the secondary cache, so the default route will no longer take effect.
  • Page 126 – The address of 0x0FFFF_FFFF, then, for this space, the access of 0x8000_0000-8FFF_FFFF is Page 157 Godson 3A1000 Processor User Manual Part 2 Prohibited. Window 6 opens all 1GB of space on memory controller 1, the system uses 0xC0000_0000 –...
  • Page 127 15.1 System memory space Loongson 3A1000 processor has two memory controllers, if the address space can be interleaved in two memories On the controller, it will bring benefits to the average access delay and average access bandwidth of the system, but it is subject to the configuration of the crossbar To limit the number of windows, certain rules must be adopted to design a certain method for address space distribution.
  • Page 128 If the memory size is 4GB, the address space of the memory in the system is as follows: starting address End address Explanation Page 159 Godson 3A1000 Processor User Manual Part 2 Address 0 0x0000_0000_0000_0000 0x0000_0000_0FFF_FFFF 0 – 256MB Address 1...
  • Page 129 4/29/2020 Godson 3A1000 Processor User Manual Page 160 Godson 3A1000 Processor User Manual Part 2 MC0 single channel 2G BASE 0x00000000_80000000 MASK 0xFFFFFFFF_80000000 MMAP 0x00000000_000000F0 Dual channel 256M x 2 BASE 0x00000000_20000000 (Interleaved with address [10]) MASK 0xFFFFFFFF_F0000400 MMAP 0x00000000_000004F0...
  • Page 130 Shot into the 0x0000_0000 space, and then one by one with the system memory mapping. In Loongson 3A1000, in order to solve the problem of DMA space conversion using large memory, the following regulations are made. (1) System memory space 0x0000_0000 – 0x0FFF_FFFF When used as DMA space, peripherals Use 0x8000_0000 –...
  • Page 131 Godson 3A1000 Processor User Manual Page 163 Godson 3A1000 Processor User Manual Part 2 16 X system memory allocation The memory allocation problem of the X system describes the video memory allocation problem. In 3A-690e, the graphics card is set It is inside the North Bridge 690E and is a device of PCIE.
  • Page 132 0x78000000, this is also achieved through TLB mapping. The code for TLB mapping is as follows: Page 164 Godson 3A1000 Processor User Manual Part 2 li t0, 15 li t3, 0xf0000000 # entry_hi, the starting address of the virtual address to be mapped...
  • Page 133 4/29/2020 Godson 3A1000 Processor User Manual Page 165 Godson 3A1000 Processor User Manual Part 2 tlbwi bnez t0, 1b // Total mapping size 16 * 16 = 256M addiu t0, t0, -1 In this way, when the graphics card accesses the video memory, we can all use the address of 0xf8000000 as the starting address of the video memory.

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