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3B3000
Loongson 3B3000 MIPS-Compatible Processor Manuals
Manuals and User Guides for Loongson 3B3000 MIPS-Compatible Processor. We have
1
Loongson 3B3000 MIPS-Compatible Processor manual available for free PDF download: User Manual
Loongson 3B3000 User Manual (128 pages)
volume One
Brand:
Loongson
| Category:
Computer Hardware
| Size: 0.5 MB
Table of Contents
Table of Contents
4
1 Overview
12
Introduction to Loongson Series Processors
12
Introduction to Godson 3A3000 / 3B3000
13
2 System Configuration and Control
15
Chip Working Mode
15
Description of Control Pins
15
Cache Consistency
17
Address Routing Distribution and Configuration
18
Chip Configuration and Sampling Register
23
3 Gs464E Processor Core
27
4 Shared Cache (Scache)
29
5 Matrix Processing Accelerator
30
6 Interruption and Communication between Processor Cores
35
7 O Interrupt
35
8 Temperature Sensor
38
Real-Time Temperature Sampling
38
High and Low Temperature Interrupt Trigger
38
High Temperature Automatic Frequency Reduction Setting
39
9 DDR2 / 3 SDRAM Controller Configuration
40
DDR2 / 3 SDRAM Controller Function Overview
40
DDR2 / 3 SDRAM Read Operation Protocol
41
DDR2 / 3 SDRAM Write Operation Protocol
41
DDR2 / 3 SDRAM Parameter Configuration Format
42
Software Programming Guide
44
Initialization
44
Control of Reset Pin
44
Leveling
46
Write Leveling
46
Gate Leveling
47
Initiate MRS Commands Separately
48
Self-Loop Test Mode Control
48
ECC Function Usage Control
49
10 Hypertransport Controller
50
Hypertransport Hardware Setup and Initialization
50
Hypertransport Protocol Support
52
Hypertransport Interrupt Support
53
Hypertransport Address Window
54
Hypertransport Space
54
Internal Window Configuration of Hypertransport Controller
54
Configuration Register
55
Bridge Control
56
Capability Registers
57
Receive Diagnostic Register
60
Interrupt Routing Mode Selection Register
61
Receive Buffer Initial Register
61
Receive Address Window Configuration Register
61
Interrupt Vector Register
64
Interrupt Enable Register
66
Interrupt Discovery & Configuration
68
POST Address Window Configuration Register
69
Prefetchable Address Window Configuration Register
70
UNCACHE Address Window Configuration Register
71
P2P Address Window Configuration Register
74
Command Send Buffer Size Register
75
Data Transmission Buffer Size Register
75
Send Buffer Debug Register
75
PHY Impedance Matching Control Register
76
Revision ID Register
77
Error Retry Control Register
77
Retry Count Register
77
Training 0 Timeout Short Timer Register
78
Training 0 Time-Out Timer Register
79
Training 1 Count Register
79
Training 2 Count Register
79
Training 3 Count Register
79
PHY Configuration Register
81
Link Initialization Debug Register
81
LDT Debug Register
82
Access Method of Hypertransport Bus Configuration Space
82
Hypertransport Multiprocessor Support
82
11 Low Speed IO Controller Configuration
84
PCI Controller
85
LPC Controller
88
UART Controller
90
Data Register (DAT)
90
Interrupt Enable Register (IER)
90
Interrupt Identification Register (IIR)
90
FIFO Control Register (FCR)
91
Line Control Register (LCR)
91
MODEM Control Register (MCR)
92
Line Status Register (LSR)
93
MODEM Status Register (MSR)
94
SPI Controller
95
Control Register (SPCR)
95
Status Register (SPSR)
96
Data Register (Txfifo)
96
External Register (SPER)
96
IO Controller Configuration
98
12 Chip Configuration Register List
101
13 Software and Hardware Design Guidelines
124
Hardware Modification Guide
124
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