Companion Chip; 32-Bit Tx System Risc; Tx39 Family; Bit Tx System Risc Tx39 Family - Toshiba TLCS-900 Family Product Manual

Companion Chip

PCI-connected companion chip
TC86C001FG (Goku-S)
Companion chip with built-in ATA and USB interfaces Companion chip with built-in ATA and USB interfaces
The TC86C001FG (GOKU-S) is a highly integrated,
high-performance interface LSI chip that supports a
widely used five interfaces. It incorporates a PCI
interface, ATA/ATAPI host controller, USB host controller,
2
USB device controller, I C bus, and serial I/O controller.
The GOKU-S facilitates designing a wide range of digital
products, including set-top boxes, PVR, information
equipment, and multifunction printers.
PCI Local Bus (32bits, 33MHz)
GOKU-S
PCI interface logic
(TC86C001)
USB
ATA/ATAPI
HOST
1ch
2ch

32-Bit TX System RISC

TX39
Family
The TX39 Family of RISC microprocessors for embedded use was developed by Toshiba based on the R3000A archi-
tecture designed by MIPS Technologies, Inc. It is an original Toshiba 32-bit processor family. Using the TX39/H or the
high-speed TX39/H2, TX39/H3 as the CPU core for gate arrays and cell-based ICs, you can accomplish a high
level of integration in your system.
High-performance RISC technology
R3000A architecture
Internal operating frequency
TX39/H: 92 MHz, TX39/H2, H3: 133 MHz
Built-in cache memory
Non-blocking load function
The instructions which follow the instruction
currently being executed are executed while the
cache is being refilled.
DSP function
32-bit multiply-accumulate (MAC) operations take
only one clock cycle to execute.
Low power consumption
Low power consumption modes
Clock stop function
8MHz
Clock
Generator
G-Bus
USB
2
I C/SIO/
DEVICE
GPIO
1ch
PCI interface
32-bit PCI bus (33 MHz)
PCI Rev. 2.2 compatible
ATA/ATAPI host controller
Single channel: Can connect up to two systems
Ultra ATA/66: Supports 66 Mbytes/s
PIO modes 0 to 4, multiword DMA modes 0, 1, 2
USB 1.1 host controller
OpenHCI 1.0a compliant
2 ports: 12 Mbits/s or 1.5 Mbits/s
Built-in overcurrent protection circuit (for each port)
USB device controller
1 port: 12 Mbits/s
2
I C bus/SIO controller
2
I C master/slave mode
UART
GPIO: 1 or 5 ports
Core operating voltage: 1.5 V
Peripheral I/O operating voltage: 3.3 V
144-pin LQFP package (20 mm x 20 mm)
Functions suitable for embedded applications
Reduced code size and improved performance
Use of branch-likely instructions
Hardware interlock function
Increased real-time capability
Cache lock function
Real-time debugger system connection
Real-time debugging is possible while cache is on.
Ideal as CPU core in embedded arrays/cell-based ICs
TX39/H2: 0.25 µm process technology
TX39/H3: 0.18 µm process technology
Complete development environment
39