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Asus Aaeon NanoCOM-APL User Manual page 12

Com express module
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Table of Contents
3.5.1 Chipset: North Bridge ............................................................................... 36
3.5.1.1
3.5.2
3.5.2.1
3.6
Setup submenu: Security ..................................................................................... 42
3.7
Setup submenu: Boot ........................................................................................... 43
3.8
Setup submenu: Save & Exit ............................................................................... 45
Chapter 4 - Drivers Installation ............................................................................................ 46
4.1
Product CD/DVD ................................................................................................... 47
Appendix A - Watchdog Timer Programming ................................................................... 49
A.1
Watchdog Timer Initial Program ........................................................................ 50
Appendix B - I/O Information .............................................................................................. 55
B.1
I/O Address Map ................................................................................................... 56
B.2
Memory Address Map ......................................................................................... 57
B.3
IRQ Mapping Chart ............................................................................................... 58
Appendix C - Programming Digital I/O.............................................................................. 59
C.1
DI/O Programming ............................................................................................... 60
C.2
Digital I/O Register ................................................................................................. 61
C.3
Digital I/O Sample Program ................................................................................ 62
Preface
North Bridge: LVDS Panel Configuration ...................... 37
Chipset: South Bridge ................................................................... 40
South Bridge: PCI Express Configuration .......................41
XII

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