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Summary of Contents for Allegro A8582
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Page 1: Evaluation Board
Demo Note for the A8582 Evaluation Board 4.7V – 40V 3.3V , 2.0A, 2MHz Asynchronous Buck Regulator Page 1 of 10 April 29, 2011... -
Page 2: General Specifications
Connect an Enable signal from EN/SYNC to GND. If the EN/SYNC input voltage is higher than 1.8V the A8582 will be enabled. If the EN/SYNC input voltage is lower than 0.8V the A8582 will be disabled. Also, EN/SYNC may be used to simultaneously enable the A8582 and synchronize the PWM switching frequency by applying a square wave above 2.2MHz. - Page 3 RPD should be used if Vout > 5.5V Empty 820pF 0603 A8582 Evaluation PCB 12Vin / 3.3Vout: RFB1 = 16.5K, RFB2 = 5.23K 15.4K, 820pF, 4.7pF: 120KHz BW, 72deg PM Note: C1 is an optional, bulk, electrolytic capacitor for general supply filtering...
- Page 4 DEMO BOARD PERFORMANCE Page 4 of 10 April 29, 2011...
- Page 5 Page 5 of 10 April 29, 2011...
- Page 6 12Vin, 2.0A Load: 0dB at 140KHz, PM=59.8deg, GM=13.7dB Iout A8582 (deg C) (deg C) (deg C) 0.25 31.3 31.0 29.5 34.8 35.4 32.5 39.9 42.9 37.2 44.9 50.6 42.8 50.9 58.6 49.3 57.7 67.8 57.3 Shorted Vout 30.0 34.9 29.0 Component Temperatures vs Load Current 12Vin, 3.3Vout, 2MHz, T...
- Page 7 Startup Shutdown 12Vin, 2.2A (1.5Ω) load 12Vin, 2.2A (1.5Ω) load CH1=Vout, CH2=COMP, CH3=EN, CH4=SS CH1=Vout, CH2=COMP, CH3=EN, CH4=SS Output Voltage Ripple Transient Response 12Vin, 2.2A (1.5Ω) load 12Vin, 0.4A to 1.5A (1.1A step) CH1=Vout (20mV/DIV) CH1=Vout, CH2=COMP, CH4=Iout Page 7 of 10 April 29, 2011...
- Page 8 SWN Voltage at 12Vin, 150mA load SWN Voltage at 12Vin, 2.2A load CH1=SWN (5V/DIV), 200ns/DIV CH1=SWN (5V/DIV), 200ns/DIV Input Voltage Ripple at 12Vin, 2.2A load Output Shorted, Hiccup Mode Operation CH1=Vin across CIN1 (50mV/DIV) CH1=Vout, CH2=COMP, CH3=SS, CH4=IL Page 8 of 10 April 29, 2011...
- Page 9 DEMO PCB LAYOUT: Top Layer and Top Silk Layer 2 and Top Silk Page 9 of 10 April 29, 2011...
- Page 10 Layer 3 and Top Silk Bottom Layer and Top Silk Page 10 of 10 April 29, 2011...
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