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Ref. No. Address
Name
S1503
(A-2)
CPU_FPGA_RECONF
S2001
(F-9)
Reset switch
S2002
(E-1)
BATT
S2003
(F-1)
HOT PLAG CONTROL
S2005
(E-3)
DD-CON CONTROL
S2502
(J-8)
APL setting switch
S4001
(G-9)
IFPLD setting switch
S4002
(F-9)
ISP selection switch
S4501
(E-7)
FPGA (IC4501)
setting switch
NSS-S2
Function
Reconfigures CPU_FPGA (IC1601).
Initializes the PU-124 board.
Turn the SRAM data backup battery ON/OFF.
ON : For normal use
OFF : For production
For debug
"2" side (the side without
) : For normal use
S2005-1 ON : 12 V → 5 V (generic) DD converter
Standby connect from ISPPAC
S2005-2 ON : 12 V → 3.3 V (generic) DD converter
Standby connect from ISPPAC
S2005-3 ON : 3.3 V → 2.5 V (DDR-DRAM)
DD converter Standby connect from
ISPPAC
S2005-4 ON : 3.3 V → 1.5 V (FPGA core)
LDO Standby connect from ISPPAC
For soft-debug (do not change except for factory
setting)
S2502-1 to 8 all OFF : For normal use
S4001-1 ON : JTAG CPU (CPU FLASH ACSESS)
S4001-2 ON : DW MODE
S4001-3 ON : M MODE
S4001-4 ON : MODE
S4001-5 :
Not used
S4001-6 :
Not used
S4001-7 ON : XWP_ACC
S4001-8 ON : IFPLD1_SEL
S4002-1 ON : ALTERA LOOP 1
S4002-2 ON : ALTERA LOOP 2
S4002-3 ON : LATTICE LOOP
S4002-4 ON : IFPLD LOOP
*4
S4002-5 ON : RS-232C
(using Max Driver IC (using CN2501))
S4002-6 to 8 : Not used
Turn on only one of the bits from S4002-1 to 4.
(Do not turn on two or more bits.)
*1 : JTAG : IFPLD1 → IFPLD2 → MPU_PLD (when connected to the MPU-136 board)
*2 : JTAG : CFPGA
*3 : JTAG : ISPPAC
*4 : JTAG : RAID_FPGA (using download tool)
For hard-debug (do not change except for factory
setting)
S4501-1 to 8 all OFF : For normal use
Factory setting
_
_
ON
"2" side
All OFF
ON
All OFF
ON
ON
*1
enable
ON
*2
enable
*3
enable
enable
All OFF
ON
1 2 3 4
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
1 2 3 4 5 6 7 8
2-3 (E)
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