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DIGITAL(MEDIA PROCESSOR) SCHEMATIC DIAGRAM
AO_D[0]
AO_SCLK
TO VIDEO IF
AO_FSYNC
AO_IEC958
SHEET 2
AO_MCLKO
AI_D[0]
VIDEO_MUTE[H]
TO 1394 PHY
PHY_CNA
480I[H]
SHEET 6
TO VIDEO IF
5
SHEET 2
B1404
B1405
TL1407
V3.3V
K1407
R1402
4
0Ω
C1450
0.1
X1401
VIDEO_27M
VI_D[2-9]
VI_D[2-9]
VO_D[0-15]
VO_D[0-15]
TO VIDEO IF
SHEET 2
R1421
DAC_CVBS_OUT
R1422
DAC_SY_OUT
R1423
DAC_SC_OUT
3
R1424
DAC_Y_OUT
R1425
DAC_PB_OUT
R1426
C1452
DAC_PR_OUT
0.1
V3.3V
VDDI1.8
R1493
0Ω
C1453
K1408
0.1
C1454
C1455
0.1
C1456
PHY_DATA[0-7]
PHY_DATA[0-7]
PHY_CTL[1]
TO 1394 PHY
PHY_CTL[0]
SHEET 6
PHY_LREQ
PHY_LPS
2
PHY_LINK_ON
PHY_CLK
DIGI3.3V
TO VIDEO IF
D2.5V
B1401
D1.8V
SHEET 2
LC1401
GND
C1401
C1402
C1404
C1405
C1406
0.1
0.1
47
0.1
0.1
B1402
LC1402
TO VIDEO IF SHEET 2
TO ATAPI IF SHEET 7
D5.0V
C1408
C1409
C1411
C1412
D5.0V
0.1
0.1
100
0.1
TO VIDEO IF
D1.8V
B1403
LC1403
D2.5V
C1415
SHEET 2
DIGI3.3V
GND
TO ATAPI IF
GND
SHEET 7
C1413
C1414
47
0.1
TO VIDEO IF SHEET 2
D3.3V
C1464
C1465
C1466
C1467
C1468
C1469
C1470
1394 PHY SHEET 6
0.1
0.1
0.1
0.1
0.1
0.1
0.1
VDDI1.8
ATAPI IF SHEET 7
GND
TO VIDEO IF
SHEET 2
1
A
TL1402
TL1437
R1408
1k
TL1403
D3.3V
TL1404
R1409
10k
R1410
10k
R1411
100
R1412
10k
R1413
10k
VI_D[2]
VI_D[3]
VI_D[4]
VI_D[5]
VI_D[6]
VI_D[7]
VI_D[8]
VI_D[9]
R1414
1k
R1415
1k
R1416
1k
R1417
1k
TL1489
R1494
10k
R1495
10k
TL1452
TL1453
TL1454
TL1455
TL1456
TL1457
TL1458
TL1459
VO_D[0]
VO_D[1]
VO_D[2]
RA1401
VO_D[3]
100
VO_D[4]
VO_D[5]
VO_D[6]
RA1402
VO_D[7]
100
VO_D[8]
VO_D[9]
VO_D[10]
RA1403
VO_D[11]
100
VO_D[12]
VO_D[13]
VO_D[14]
RA1404
VO_D[15]
100
R1419
100
TL1412
TL1490
TL1491
R1420
100
R1485
R1486
R1487
R1488
R1489
R1490
D1401
D1402
1SS355-X
1SS355-X
TL1413
TL1414
TL1415
R1491
1k
TL1417
TL1418
TL1419
R1427
100
TL1420
PHY_DATA[7]
PHY_DATA[6]
PHY_DATA[5]
RA1405
PHY_DATA[4]
100
PHY_DATA[3]
PHY_DATA[2]
PHY_DATA[1]
RA1406
PHY_DATA[0]
100
R1428
100
R1429
100
R1430
100
R1431
100
R1432
K1402
C1442
0.1
C1417
C1418
C1419
C1420
C1421
C1422
C1423
C1424
C1425
K1403
0.1
0.1
10
0.1
0.1
0.1
0.1
0.1
SSTL2_VDD
K1404
C1427
C1428
C1429
C1430
10
0.1
0.1
0.1
K1401
C1461
C1463
K1405
0.1
0.1
C1416
0.1
C1434
C1435
C1436
C1437
C1438
C1439
C1445
10
0.1
0.1
0.1
0.1
0.1
C1471
C1472
C1473
C1474
0.1
0.1
0.1
0.1
TO ATAPI IF
TO DDR SDRAM
SHEET 7
SHEET 5
B
C
IC1401
DMN8652-BOL
C1444
0.1
K1406
C1446
0.1
NOT
NOT
USED
USED
D
E
2-11
2-12
R1471
100
R1470
1k
R1472
0Ω
R1469
1k
C1459
R1468
100
R1467
100
R1466
100
R1465
100
R1464
100
TL1485
R1462
100
R1461
100
R1460
100
R1459
100
R1458
100
TL1484
TL1483
100
R1455
TL1481
R1453
100
CS[1]
R1452
100
CS[0]
TL1480
TL1479
TL1478
TL1477
R1451
MADD[22]
100
R1450
MADD[5]
100
MADD[4]
RA1411
MADD[3]
100
MADD[2]
MADD[1]
MADD[21]
RA1410
MADD[20]
100
MADD[19]
MADD[18]
MADD[17]
RA1409
MADD[16]
100
MADD[15]
MADD[14]
MADD[13]
RA1408
MADD[12]
100
MADD[11]
MADD[10]
MADD[9]
RA1407
MADD[8]
100
MADD[7]
MADD[6]
ATA_ADD[0]
ATA_ADD[1]
ATA_ADD[2]
ATA_ADD[3]
ATA_ADD[4]
ATA_DAT[15]
ATA_DAT[14]
ATA_DAT[13]
ATA_DAT[12]
ATA_DAT[11]
ATA_DAT[10]
ATA_DAT[9]
ATA_DAT[8]
ATA_DAT[7]
ATA_DAT[6]
ATA_DAT[5]
ATA_DAT[4]
ATA_DAT[3]
ATA_DAT[2]
ATA_DAT[1]
ATA_DAT[0]
ATA2_ADD[0]
ATA2_ADD[1]
ATA2_ADD[2]
ATA2_ADD[3]
ATA2_ADD[4]
ATA2_DAT[15]
ATA2_DAT[14]
ATA2_DAT[13]
ATA2_DAT[12]
ATA2_DAT[11]
ATA2_DAT[10]
ATA2_DAT[9]
ATA2_DAT[8]
ATA2_DAT[7]
ATA2_DAT[6]
ATA2_DAT[5]
ATA2_DAT[4]
ATA2_DAT[3]
ATA2_DAT[2]
ATA2_DAT[1]
ATA2_DAT[0]
R1441
10k
C1457
C1458
0.1
0.1
TO
TO
TO VIDEO IF
VIDEO IF
JUNCTION
SHEET 2
SHEET 2
(VIDEO)
SHEET 23
F
SDRAM_A[14-17]
SDRAM_A[14-17]
SDRAM_VREF
SDRAM_CLK_L[1]
SDRAM_CLK_L[1]
SDRAM_CLK[1]
SDRAM_CLK[1]
SDRAM_CLK_L[0]
SDRAM_CLK_L[0]
SDRAM_CLK[0]
SDRAM_CLK[0]
SDRAM_WE_L
TO DDR SDRAM
SDRAM_WE_L
SDRAM_CKE
SDRAM_CKE
SHEET 5
SDRAM_RAS_L
SDRAM_RAS_L
SDRAM_CAS_L
SDRAM_CAS_L
SDRAM_DQM[0-3]
SDRAM_DQM[0-3]
SDRAM_DQS[0-3]
SDRAM_DQS[0-3]
SDRAM_A[0-13]
SDRAM_A[0-13]
SDRAM_DQ[16-31]
SDRAM_DQ[16-31]
SDRAM_DQ[0-15]
SDRAM_DQ[0-15]
ALE
OE[L]/LDS[L]
UWE[L]/UDS[L]
ELINK_INT[L]
EPG_INT[L]
TO
RD/WR[L]
WAIT[L]
FLASH MEMORY
DTACK[L]
SHEET 3
CS[3]
CS[1]
CS[0]
MADD[22]
MADD[1-5]
MADD[1-5]
MADD[6-21]
MADD[6-21]
TO 1394 PHY
PHY_RESET[L]
SHEET 6
TO VIDEO IF
DAC_RST[L]
SHEET 2
ATA_ADD[0-4]
ATA_ADD[0-4]
ATA_DAT[0-15]
ATA_DAT[0-15]
ATA_RESET
ATA_DMAACK[L]
ATA_DMARQ
ATA_IORDY
ATA_INTRQ
ATA_DIOR[L]
TO ATAPI IF
ATA_DIOW[L]
SHEET 7
ATA2_RESET
ATA2_DMAACK[L]
ATA2_DMARQ
ATA2_IORDY
ATA2_INTRQ
ATA2_DIOR[L]
ATA2_DIOW[L]
ATA2_ADD[0-4]
ATA2_ADD[0-4]
ATA2_DAT[0-15]
ATA2_DAT[0-15]
R1445
100
K_BUS_CLK
R1446
100
K_BUS_REQ
TO VIDEO IF
R1447
100
SYS_RESET[L]
SHEET 2
R1448
100
K_BUS_OUT
D1403
R1449
100
K_BUS_IN
TO
E5_RESET[L]
FLASH MEMORY
UART2_TX
UART2_RX
SHEET 3
p10658001a_rev0
SHEET 4
G
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