Agilent Technologies 33250A Service Manual page 105

Chapter 5 Theory of Operation
Digital Waveform Translator
Edge speed range is set by TR_RNG(4:1) which control transistors Q1603
through Q1606. If a transistor is off, the associated integrating capacitor
(C1610 through C1613) floats and is effectively out of the circuit. If a
transistor is on, however, one end of the its capacitor is grounded and
capacitor is switched into the circuit.
U1602 converts the –0.8 V to –1.6 V to ±0.64 V levels. The upper clamp
voltage of –1.0 V is obtained from resistive divider R1613 and R1616 and
the VEE (–5.2 V) supply. The lower clamp level of –1.6 V is obtained from
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resistive divider R1628 and R1631 and VEE.
The Schottky-diode bridge (CR1601 and CR1602) switches one of two
current sources into the capacitive charge circuit. The current source
used is set by the +0.64 V to –0.64 V input from level shifter U1602.
The two current sources are similar. They are controlled by the System
DAC signals V_LEDGE and V_TEDGE.
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The V_LEDGE input varies from +65 mV to +1.95 V. This input range is
applied through amplifier U1601-B to Q1602 where it varies the current
through R1614 from 0.25 mA to 7.5 mA.
This varying current is applied to a current mirror consisting of U1601-A
and Q1601. The Schottky-diode bridge the steers this current in to the
integration capacitor.
There are five integration capacitors: C1609 through C1613. C1609 is
always in the circuit (<10 ns) and the other four are switched in response
to signals from the Main Gate Array (TR_RNG[4:1]).
The value on the integration capacitor is amplified to +1.1 V to –1.1 V
levels by clamp amplifier U1605. V_REF is used by U1604 to set the
upper and lower clamping levels.
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