ON Semiconductor AR0330CS Manual

1/3-inch cmos digital image sensor

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AR0330CS
AR0330CS and AR0330SR
1/3-Inch CMOS Digital
Image Sensor
General Description
The AR0330CS can be operated in its default mode or programmed
for frame size, exposure, gain, and other parameters. The default mode
output is a 2304 x 1296 image at 30 frames per second (fps). The
sensor outputs 10− or 12−bit raw data, using either the parallel or serial
(MIPI) output ports.
The ON Semiconductor AR0330CS is a 1/3−inch CMOS digital
image sensor with an active−pixel array of 2304 (H) x1536 (V). It can
support 3.15 megapixel (2048H x 1536 V) digital still image capture
and a 1080p30 +20%EIS (2304H x 1296 V) digital video mode. It
incorporates sophisticated on−chip camera functions such as
windowing, mirroring, column and row subsampling modes, and
snapshot modes.
Table 1. KEY PARAMETERS
Parameter
Optical Format
Active Pixels
Pixel Size
Color Filter Array
Shutter Type
Input Clock Range
Output Clock Maximum
(CLK_OP)
Responsivity
Power Consumption
SNR
MAX
Dynamic Range
Supply
I/O/Digital
Voltage
Digital
Analog
Operating Temperature
(junction) −T
J
Package Options
© Semiconductor Components Industries, LLC, 2012
January, 2019 − Rev. 8
Typical Value
1/3−inch (6.0 mm)
Entire Array: 6.09 mm
Still Image: 5.63 mm (4:3)
HD Image: 5.82 mm (16:9)
2304(H) x 1536(V): (Entire Array):
5.07 mm (H) x 3.38 mm (V)
2048(H) x 1536(V) (4:3, Still Mode)
2304(H) x 1296(V) (16:9, sHD Mode)
2.2 mm x 2.2 mm
RGB Bayer
ERS and GRR
6 – 27 MHz
98 Mp/s (Parallel, MIPI)
2.0 V/lux−sec
1080P30 MIPI Mode: 282 mW
1080P30 Parallel Mode: 252 mW
39 dB
69.5 dB
1.7–1.9 V (1.8 V Nominal) or
2.4–3.1 V (2.8 V Nominal)
1.7–1.9 V (1.8 V Nominal)
2.76–2.9 V
–30°C to + 70° C
6.28 mm x 6.65 mm CSP
11.43 mm x 11.43 mm PLCC
PLCC48
11.43x11.43
CASE 776AM
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
Features
(continued)
2.2 mm Pixel with ON Semiconductor
A−Pix
technology
Superior Low−light Performance
3.5 Mp Active Array, 2.9 Mp (16:9) Video
3.4 Mp (3:2) and 3.15 Mp (4:3) Still Images
Support for External Mechanical Shutter
Support for External LED or Xenon Flash
Data Interfaces: Two−lane Serial MIPI or
Parallel Interface
On−chip phase−locked Loop (PLL)
Oscillator
Integrated Position−based Color and Lens
Shading Correction
Simple Two−wire Serial Interface
Auto Black Level Calibration
12−to−10 bit Output A−Law Compression
Slave Mode for Precise Frame−rate Control
and for Synchronizing Two Sensors
Applications
1080P30 High−definition Digital Video
Camcorder
Web Cameras and Video Conferencing
Cameras
Security
1
www.onsemi.com
ODCSP64
6.278x6.648
CASE 570BH
Publication Order Number:
AR0330CS/D

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  • Page 1 1/3-Inch CMOS Digital Image Sensor General Description The AR0330CS can be operated in its default mode or programmed www.onsemi.com for frame size, exposure, gain, and other parameters. The default mode output is a 2304 x 1296 image at 30 frames per second (fps). The sensor outputs 10−...
  • Page 2: Ordering Information

    3.5 MP, 1/3− inch, 12 Deg CRA, Parallel, MIPI, CSP Evaluation board FUNCTIONAL OVERVIEW The AR0330CS is a progressive−scan sensor that between 6 and 27 MHz. The maximum CLK_OP is 98 Mp/s generates a stream of pixel data at a constant frame rate. It using MIPI serial interface and 98 Mp/s using the parallel uses an on−chip, phase−locked loop (PLL) that can generate...
  • Page 3: Working Modes

    AR0330CS WORKING MODES The AR0330CS sensor working modes are specified from the following aspect ratios: Table 3. AVAILABLE ASPECT RATIOS IN THE AR0330CS SENSOR Aspect Ratio Sensor Array Usage Still Format #1 2256(H) x 1504(V) Still Format #2 2048 (H) x 1536 (V)
  • Page 4 4. The pull−up resistor is not required if the controller drives a valid logic level on S at all times. 5. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is minimized.
  • Page 5 15. The pull−up resistor is not required if the controller drives a valid logic level on S at all times. 16. ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the digital power planes is minimized.
  • Page 6: Pin Descriptions

    AR0330CS PIN DESCRIPTIONS Table 5. PIN DESCRIPTIONS Name Type Description RESET_BAR Input Asynchronous reset (active LOW). All settings are restored to factory default EXTCLK Input Master input clock, range 6 − 27 MHz TRIGGER Input Receives slave mode VD signal for frame rate synchronization and trigger to start a GRR frame Input Two−wire serial address select...
  • Page 7 AR0330CS Table 6. AR0330CS CSP (PARALLEL/MIPI) PACKAGE PINOUT HV_NPIX FRAME_VALID TEST SHUTTER DATA FLASH LINE_VALID TRIGGER RESET_BAR ADDR EXTCLK DATA_N PIXCLK CLK_N DATA_P – – CLK_P _PLL DATA2_N – _MIPI DATA2_P _MIPI 22. NC = Do not connect. For manufacturing test purpose only.
  • Page 8 32 OE_BAR 11 17 31 TEST 10 18 TOP VIEW Figure 4. PLCC Pinout Table 8. AR0330CS PLCC PACKAGE THERMAL RESISTANCE Using JEDEC 1S0P Board Using JEDEC 2S2P Board Junction to ambient air thermal resistance (qJA) (°C/W) 51.47 36.92 Junction to board thermal resistance (qJB) (°C/W) 22.16...
  • Page 9: Sensor Initialization

    AR0330CS SENSOR INITIALIZATION Power−Up Sequence The recommended power−up sequence for 7. Wait 150,000 EXTCLKs (for internal initialization AR0330CS is shown in Figure 5. The available power into software standby supplies (V IO, V _PLL, V _MIPI, V PIX) 8. Write R0x3052 = 0xA114 to configure the internal must have the separation specified below.
  • Page 10 PLL in the CSP package and must be powered to 2.8 V. Power−Down Sequence The recommended power−down sequence for the 2. The soft standby state is reached after the current AR0330CS is shown in Figure 6. The available power row or frame, depending on configuration, has supplies (V IO, V _PLL, V _MIPI., V...
  • Page 11: Standby Mode

    AR0330CS STANDBY MODE Soft Standby Hard Standby 1. Disable streaming by setting standby R0x301a[2] 1. Disable streaming by setting standby R0x301a[2] 2. Delay 10 ms 2. Delay 10 ms 3. Stop EXTCLK; pull EXTCLK pin LOW 3. Pull RESET_BAR to LOW ELECTRICAL CHARACTERISTICS Table 11.
  • Page 12 AR0330CS Table 13. STANDBY POWER = 24 MHz; V = 1.8 V; V _IO = 1.8 V; V = 2.8 V; V _PIX = 2.8 V; EXTCLK _PLL = 2.8 V; Output load = 68.5 pF; T = 60°C Power...
  • Page 13 AR0330CS Table 15. TWO−WIRE SERIAL BUS CHARACTERISTICS = 27 MHz; V = 1.8 V; V IO = 2.8 V; V = 2.8 V; V PIX = 2.8 V; V PLL = 2.8 V; T = 25°C EXTCLK Standard Mode Fast Mode...
  • Page 14 AR0330CS t RP t FP 90 % 90 % 10 % 10 % t EXTCLK EXTCLK t CP PIXCLK t PD t PD Data[11:0] Pxl _ 0 Pxl _ 1 Pxl _ 2 Pxl _ n t PFH t PFL...
  • Page 15 AR0330CS ELECTRICAL DEFINITIONS Figure 9 is the diagram defining differential amplitude MIPI PHY to constant Logic 1 and Logic 0. Measure V and rise and fall times. To measure V and V with voltmeters for both Logic 1 and Logic 0.
  • Page 16 AR0330CS (1) * V (eq. 6) Both V and V are measured for all output channels. shown in Figure 9: “Single−Ended and Differential The worst case is defined as the largest difference in Signals” between all channels regardless of logic level. And the 3.
  • Page 17 AR0330CS Figure 12 also shows the corresponding AC V measured as the absolute peak deviation from the mean DC common−mode signal. Differential skew between the V common−mode. and V signals can cause spikes in the common−mode, Transmitter Eye Mask which the receiver needs to be able to reject. V CM_AC 1.3 * V...
  • Page 18 1. Place the sensor in standby order to achieve faster frame rates. Instructions for 2. Write 0xC000 to R0x3088 (“seq_ctrl_port”) shortening the sequencer can be found in the AR0330CS 3. Sequentially read 2−bytes at a time from R0x3086 Developer Guide.
  • Page 19 AR0330CS SENSOR PLL pre_pll_clk_div pll_multiplier EXTCLK 2 (1−64) F VCO 58 (32−384) (6−27 MHz) Figure 16. Relationship Between Readout Clock and Peak Pixel Rate The sensor contains a phase−locked loop (PLL) that is required for the sensor array, the pixel analog and digital used for timing generation and control.
  • Page 20 AR0330CS The maximum output of the parallel interface is 98 (CLK_PIX) to 49 MHz. The sensor will not use the F SERIAL Mpixel/s (CLK_OP). This will limit the readout clock when configured to use the parallel interface. SERIAL_CLK Table 19. PLL PARAMETERS FOR THE PARALLEL INTERFACE...
  • Page 21 AR0330CS Table 21. PLL PARAMETERS FOR THE SERIAL INTERFACE Parameter Symbol Unit External Clock EXTCLK VCO Clock Readout Clock CLK_PIX Output Clock CLK_OP Mpixel/s 384 (MIPI) 768 (MIPI) Mbps Output Serial Data Rate Per Lane SERIAL 192 (MIPI) 384 (MIPI)
  • Page 22 AR0330CS Table 23. OUTPUT ENABLE CONTROL OE_BAR Pin Drive Signals R0x301A–B[6] Description Disabled Interface High−Z Disabled Interface driven Interface High−Z Interface driven Interface driven Configuration of the Pixel Data Interface Fields in R0x301A are used to configure the operation of the pixel data interface.
  • Page 23 AR0330CS enabled (reset_register[12] = 0). The following serial The serial_format register (R0x31AE) register controls formats are supported: which serial interface is in use when the serial interface is • 0x0201 – Sensor supports single−lane MIPI operation enabled (reset_register[12] = 0). The following serial •...
  • Page 24 + fine_inegration_time clk_pix FINE The maximum allowed value for fine_integration_time is Semiconductor recommends that line_length_pck − 1204. fine_integration_time in the AR0330CS be left at zero. Vertical Blanking = frame_length_lines x T = coarse_integration_time x T FRAME COARSE Read 16.6 ms = 1308 rows x 12.7 ms/row...
  • Page 25 AR0330CS The minimum frame−time is defined by the number of set to a value equal to or greater than the frame_length_lines. row periods per frame and the row period. The sensor The maximum integration time can be limited to the frame frame−time will increase if the coarse_integration_time is...
  • Page 26: Gain Stages

    AR0330CS GAIN STAGES The analog gain stages of the AR0330CS sensor are will apply the same analog gain to each color channel. shown in Figure 24. The sensor analog gain stage consists of Digital gain can be configured to separate levels for each column amplifiers and a variable ADC reference.
  • Page 27 AR0330CS Refer to “Real−Time Context Switching” for the analog and digital gain registers in both context A and context B modes. www.onsemi.com...
  • Page 28 This is the normal mode of operation. When the 2. Global reset mode AR0330CS is streaming; it generates frames at a This mode can be used to acquire a single image at fixed rate, and each frame is integrated (exposed) the current resolution.
  • Page 29 2x2 or 3x3 either skipping or binning pixels within the readout window. subsampling. Figure 27. Horizontal Binning in the AR0330CS Sensor Horizontal binning is achieved either in the pixel readout or the digital readout. The sensor will sample the combined 2x or 3x adjacent pixels within the same color plane.
  • Page 30 AR0330CS Figure 28. Vertical Row Binning in the AR0330CS Sensor Vertical row binning is applied in the pixel readout. Row read together. As well, that the sensor will read a Gr−R row binning can be configured of 2x rows within the same color first followed by a B−Gb row.
  • Page 31 AR0330CS Table 30. CONFIGURATION FOR VERTICAL SUBSAMPLING y_odd_inc Restrictions: No subsampling y_odd_inc = 1 The horizontal FOV must be programmed to meet the following rule: skip = (1 + 1) × 0.5 = 1x y_addr_end * y_addr_start ) 1 + even number...
  • Page 32: Sensor Frame Rate

    OB rows read per frame, two (eq. 3) embedded data rows, and two blank rows. 1116(ADC_HIGH_SPEED) + 1 (0) Options to modify this limit, as mentioned in the “Sequencer” section, can be found in the AR0330CS Developer Guide. y_addr_end * y_addr_start (eq. 6) Minimumframe_length_lines +...
  • Page 33 AR0330CS Table 31. Minimum Vertical Blanking Configuration R0x3180[0x00F0] OB Rows minimum_vertical_blanking 0x8 (Default) 8 OB Rows 8 OB + 4 = 12 4 OB Rows 4 OB + 4 = 8 2 OB Rows 2 OB + 4 = 6...
  • Page 34: Slave Mode

    AR0330CS SLAVE MODE The slave mode feature of the AR0330CS supports updates. The VD signal is input to the trigger pin. Both the triggering the start of a frame readout from a VD signal that GPI_EN (R0x301A[8]) SLAVE_MODE is supplied from an external ASIC. The slave mode signal (R0x30CE[4]) bits must be set to “1”...
  • Page 35 AR0330CS Frame Valid Rising Rising Rising Edge Edge Edge VD Signal Slave Mode Row Reset Inactive Active Inactive Active Trigger (start of integration) Row reset and read Rising edge of VD Row Readout operations begin signal triggers the start after the rising edge of the frame readout.
  • Page 36 VD period. To increase integration 16.6 ms while the integration time is configured to 8.33 ms. time more than current VD period, the AR0330CS must be When the slave mode becomes active, the sensor will configured to work at a lower frame rate and read out image pause both row read and row reset operations.
  • Page 37 Table 32. SERIAL SYNC CODES INCLUDED WITH EACH PROTOCOL INCLUDED WITH THE AR0330CS SENSOR Start of Vertical Start of Frame...
  • Page 38 RED_GAIN 0x305A RED_GAIN_CB 0x30C0 GREEN2_GAIN 0x305C GREEN2_GAIN_CB 0x30C2 GLOBAL_GAIN 0x305E GLOBAL_GAIN_CB 0x30C4 39. ON Semiconductor recommends leaving fine_integration_time at 0. 1/60s 1/60s Row Reset Row Read Row Reset Row Read Vertical Blanking Active Rows Time Row Reset Row Read Row Reset...
  • Page 39: Test Patterns

    1024 to 2047 2048 to 4095 TEST PATTERNS The AR0330CS has the capability of injecting a number Test_Pattern_Mode register according to Table 35. When of test patterns into the top of the datapath to debug the test patterns are enabled the active area will receive the value digital logic.
  • Page 40 [0] indicates the data transfer direction. A “0” in bit sends a no−acknowledge bit. [0] indicates a WRITE, and a “1” indicates a READ. The default slave addresses used by the AR0330CS sensor are Single READ From Random Location 0x20 (write address) and 0x21 (read address). Alternate...
  • Page 41 The master terminates the READ by generating a This sequence (Figure 35) performs a read using the no−acknowledge bit followed by a stop condition. The current value of the AR0330CS internal register address. figure shows two independent READ sequences. Previous Reg Address, N...
  • Page 42: Spectral Characteristics

    AR0330CS Figure 38. Single WRITE to Random Location SPECTRAL CHARACTERISTICS Figure 39. Bare Die Quantum Efficiency www.onsemi.com...
  • Page 43 AR0330CS Table 36. CHIEF RAY ANGLE (CRA) 12 5 Image Height deg. 0.152 0.305 1.66 0.457 2.54 0.609 3.42 0.761 4.28 0.914 5.11 1.066 5.94 1.218 6.75 1.371 7.57 1.523 8.37 1.675 9.16 1.828 9.90 1.980 10.58 2.132 11.15 2.284 11.57...
  • Page 44 AR0330CS PACKAGE ORIENTATION IN CAMERA DESIGN In a camera design, the package should be placed in a PCB that the image captured using a lens will be oriented so that the first clear pixel is located at the bottom left of the correctly.
  • Page 45: Package Dimensions

    DRAWING TO COME 98AON94058F DOCUMENT NUMBER: Electronic versions are uncontrolled except when accessed directly from the Document Repository. Printed ON SEMICONDUCTOR STANDARD STATUS: versions are uncontrolled except when stamped “CONTROLLED COPY” in red. REFERENCE: © Semiconductor Components Industries, LLC, 2002 http://onsemi.com...
  • Page 46 30 DEC 2014 DUCTOR. REQ. BY D. TRUHITTE. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
  • Page 47 ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
  • Page 48 FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized...

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