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ON Semiconductor KAC-12040 Manual

4000 (h) x 3000 (v) cmos image sensor
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KAC-12040
4000 (H) x 3000 (V)
CMOS Image Sensor
Description
The KAC−12040 Image Sensor is a high-speed 12 megapixel
CMOS image sensor in a 4/3" optical format based on a 4.7 mm 5T
CMOS platform. The image sensor features very fast frame rate,
excellent NIR sensitivity, and flexible readout modes with multiple
regions of interest (ROI). The readout architecture enables use of 8, 4,
or 2 LVDS output banks for full resolution readout of 70 frames per
second.
Each LVDS output bank consists of up to 8 differential pairs
operating at 160 MHz DDR for a 320 Mbps data rate per pair.
The pixel architecture allows rolling shutter operation for motion
capture with optimized dynamic range or global shutter for precise
still image capture.
Table 1. GENERAL SPECIFICATIONS
Parameter
Architecture
Resolution
Aspect Ratio
Pixel Size
Total Number of Pixels
Number of Effective Pixels
Number of Active Pixels
Active Image Size
Master Clock Input Speed
Maximum Pixel Clock Speed
Number of LVDS Outputs
Number of Output Banks
Frame Rate, 12 Mp
Charge Capacity
Quantum Efficiency
KAC−12040−CBA
KAC−12040−ABA
Read Noise
(at Maximum LVDS Clock)
Dynamic Range
Blooming Suppression
Image Lag
Digital Core Supply
Analog Core Supply
Pixel Supply
Power Consumption
Package
Cover Glass
NOTE: All Parameters are specified at T = 40°C unless otherwise noted.
© Semiconductor Components Industries, LLC, 2016
March, 2016 − Rev. 5
Typical Value
5T Global Shutter CMOS
12 Megapixels
4:3
4.7 mm (H) × 4.7 mm (V)
4224 (H) × 3192 (V)
4016 (H) × 3016 (V)
4000 (H) × 3000 (V)
18.8 mm (H) × 14.1 mm (V)
23.5 mm (Diagonal), 4/3" Optical Format
5 MHz to 50 MHZ
160 MHz DDR LVDS, 320 Mbps
64 Differential Pairs
8, 4, or 2
1−70 fps 10 bits
1−75 fps 8 bits
16,000 electrons
40%, 47%, 45% (470, 540, 620 nm)
53%, 15%, 10% (500, 850, 900 nm)
−
3.7 e
rms, Rolling Shutter
−
25.5 e
rms, Global Shutter
73 dB, Rolling Shutter
56 dB, Global Shutter
> 10,000x
1.3 electron
2.0 V
1.8 V
2.8 V & 3.5 V
1.5 W for 12 Mp @ 70 fps 10 bits
267 Pin Ceramic Micro-PGA
AR Coated, 2-sides
Figure 1. KAC−12040 CMOS Image Sensor
Features
•
Global Shutter and Rolling Shutter
•
Very Fast Frame Rate
•
High NIR Sensitivity
•
Multiple Regions of Interest
•
Interspersed Video Streams
Applications
•
Machine Vision
•
Intelligent Transportation Systems
•
Surveillance
ORDERING INFORMATION
See detailed ordering and shipping information on page 2 of
this data sheet.
1
www.onsemi.com
Publication Order Number:
KAC−12040/D

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Summary of Contents for ON Semiconductor KAC-12040

  • Page 1 KAC-12040 4000 (H) x 3000 (V) CMOS Image Sensor Description The KAC−12040 Image Sensor is a high-speed 12 megapixel CMOS image sensor in a 4/3″ optical format based on a 4.7 mm 5T CMOS platform. The image sensor features very fast frame rate, www.onsemi.com...

  • Page 2: Ordering Information

    Lens Mount Kit that Supports C, CS, and F Mount Lenses. Includes IR Cut-filter for Color Imaging. See the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming convention used for image sensors. For reference documentation, including information on evaluation kits, please visit our web site at www.onsemi.com.

  • Page 3: Device Description

    KAC−12040 DEVICE DESCRIPTION Architecture 3.5 V LVDS Bank 3 LVDS Bank 5 LVDS Bank 7 3.3 V 2.8 V Odd Row ADC, Analog Gain, Black-Sun Correction 2.0 V 1.8 V − 1D Chip Clock (2 Pins) TRIGGER RESETN 4000 (H) y 3000 (V) Clk1 4.7 mm Pixel Serial...

  • Page 4: Physical Orientation

    KAC−12040 Physical Orientation LVDS Bank 3 LVDS Bank 5 LVDS Bank 7 LVDS Bank 2 LVDS Bank 4 LVDS Bank 6 Notes: 1. The center of the pixel array is aligned to the physical package center. 2. The region under the sensor die is clear of pins enabling the use of a heat sink. 3.
  • Page 5 KAC−12040 Table 4. PRIMARY PIN DESCRIPTION Name Type Description AB09 RESETN Sensor Reset (0 V = Reset State) CLK_In1 Sensor Input Clk_In1 (45−50 MHz) CLK_In2 Sensor Input Clk_In2 (Connect to Clk1) AB08 TRIGGER Trigger Input (Optional) AA05 SCLK SPI Master Clock AA08 MOSI SPI Master Output, Slave Input...
  • Page 6 KAC−12040 Table 6. LVDS PIN DESCRIPTION Name Description Name Description Name Description Name Description 1DCLK+ 3DCLK+ 5DCLK+ 7DCLK+ Bank 1 Bank 3 Bank 5 Bank 7 LVDS Clock LVDS Clock LVDS Clock LVDS Clock 1DCLK− 3DCLK− 5DCLK− 7DCLK− 1DATA0+ 3DATA0+ 5DATA0+ 7DATA0+ 1DATA0−...

  • Page 7: Imaging Performance

    KAC−12040 IMAGING PERFORMANCE Table 7. TYPICAL OPERATIONAL CONDITIONS (Unless otherwise noted, the Imaging Performance Specifications are measured using the following conditions.) Description Condition Notes Light Source Continuous Red, Green and Blue LED Illumination Temperature Measured Die Temperature: 40°C and 27°C Integration Time 16.6 ms (1400d LL, Register 0201h) Readout Mode...
  • Page 8 KAC−12040 Table 10. PERFORMANCE SPECIFICATIONS ALL CONFIGURATIONS Temperature Sampling Tested at Plan (5C) Description Symbol Min. Nom. Max. Unit Test Notes − Photodiode Charge − − 27, 40 Capacity − − Read Noise − 3.7 RS − − 25.5 GS −...
  • Page 9 KAC−12040 TYPICAL PERFORMANCE CURVES Figure 4. Monochrome QE (with Microlens) Figure 5. Bayer QE (with Microlens) www.onsemi.com...
  • Page 10 KAC−12040 Angular Quantum Efficiency For the curves marked “Horizontal”, the incident light angle is varied along the wider array dimension. For the curves marked “Vertical”, the incident light angle is varied along the shorter array dimension. Figure 6. Monochrome Relative Angular QE (with Microlens) Figure 7.
  • Page 11 KAC−12040 Dark Current vs. Temperature NOTE: “Dbl” denotes an approximate doubling temperature for the dark current for the displayed temperature range. Figure 8. Dark Current vs. Temperature Power vs. Frame Rate The most effective method to use the maximum PLL2 operations are suspended during Vertical Blanking speed (313 →...
  • Page 12 KAC−12040 Power and Frame Rate vs. ADC Bit Depth Increasing the ADC bit depth impacts the frame rate by shows the power and Frame rate range for several typical changing the ADC conversion time. The following figure cases. Figure 10. ADC Bit Depth Impact on Frame Rate and Power www.onsemi.com...
  • Page 13 KAC−12040 DEFECT DEFINITIONS Table 11. OPERATION CONDITIONS FOR DEFECT TESTING Description Condition Notes Operational Mode 10 bit ADC, 8 LVDS Outputs, Global Shutter and Rolling Shutter Modes, Dual-Scan, Black Level Clamp ON, Column/Row Noise Corrections ON, 1× Analog Gain, 1× Digital Gain Pixels per Line 4,000 Lines per Frame...
  • Page 14 KAC−12040 TEST DEFINITIONS Test Regions of Interest Image Area ROI: Pixel (0, 0) to Pixel (4015, 3015) Active Area ROI: Pixel (8, 8) to Pixel (3999, 2999) Center ROI: Pixel (1958, 1458) to Pixel (2057, 1557) Only the Active Area ROI pixels are used for performance and defect tests. 4000 (H) y 3000 (V) 4.7 mm Pixel Figure 11.
  • Page 15 KAC−12040 or equal to the median value of that region of interest minus 7) Black-Sun Anti-Blooming the dark threshold specified. A typical CMOS image sensor has a light response profile Example for bright field defective pixels: that goes from 0 dn to saturation (1023 dn for KAC−12040 •...
  • Page 16 KAC−12040 • Analog gain is set to 8. With no illumination a 64 average The integration time is varied until the integration time dark image is recorded (Dark_ref). The ‘el-per-DN’ is required to reach the 70% saturation is determined. measured using the photon transfer method. = the active array mean at the 70% saturation Illumination is adjusted blink every other frame such that integration time.

  • Page 17: Operation

    KAC−12040 OPERATION This section is a brief discussion of the most common All SPI reads are to an even address, all SPI writes are to an features and functions assuming default conditions. See the odd address. KAC−12040 User Guide for a full explanation of the sensor Sensor States operation modes, options, and registers.
  • Page 18 KAC−12040 Encoded Syncs the following Figure 13. This is performed for each of the To facilitate system acquisition synchronization the 8 LVDS output banks providing frame, line, and output KAC−12040 places synchronization words (SW) at the synchronization. See the KAC−12040 User Guide for beginning and at the end of each output row as indicated in additional detail on LVDS and Encoded Sync output.
  • Page 19 KAC−12040 Frame Time By default the Integration Phase overlaps the Readout and The frame time is defined in units of Line Time. 1 Line Frame Wait Phases. If the Integration Phase is larger than the Time unit = 2 output rows. To first-order the frame rate is not Readout + Frame Wait time, then the Integration Phase will directly impacted by selection of Global Shutter, Rolling determine the video frame rate.
  • Page 20 KAC−12040 Global Shutter Readout Global Shutter readout provides the maximum precision Global Shutter readout mode is selected using Bits [1:0] for freezing scene motion. Any motion artifacts will be of Register 01D1h. 100% defined by an ideal integration time edge. Every pixel Images can be initiated by setting and holding the in the array starts and stops integration at the same time.
  • Page 21 KAC−12040 Rolling Shutter Readout The KAC−12040 high speed Rolling Shutter readout of the array to the bottom. In the Figure 18 frame time provides the maximum dynamic range while still providing illustration this ‘moving shutter’ displays as a sloped edge excellent motion capture.
  • Page 22 KAC−12040 8 BANK LVDS DATA READOUT LVDS Banks period. All 7 data pairs, of each bank, are used only in 14 bit The KAC−12040 provides 8 parallel pixel banks, each operation mode. By default only 5 data pairs are used for 10 bit mode (D4 →...
  • Page 23 KAC−12040 8 Bank Pixel Order The KAC−12040 always processes two rows at a time. 4. Each LVDS Bank outputs one pixel per clock Even row decodes are sent to the bottom ADC and LVDS cycle, so 4 pixels of each row are output each full output banks (0, 2, 4, 6).
  • Page 24 KAC−12040 De-Serializer Settings Figure 21 shows the data stream of one LVDS bank for The SOL/SOF synchronization words are sent out of each 10 bit resolution. LVDS bank before the first valid pixel data from that bank. Data serialization is fixed at 2 cycle DDR for all bit depths. Each bank outputs all 4 syncs of the SOF or SOL.

  • Page 25: Register Definition

    KAC−12040 REGISTER DEFINITION Table 15. REGISTER DEFINITION 16 bit Default Value Write Address (Hex) Hex/Dec SPI State Group Register Name 0001 420d Frame A Definition Frame A ROI y1 0009 2176d Frame A Definition Frame A ROI h1 0011 Frame A Definition Frame A ROI x1 0019 3856d...
  • Page 26 KAC−12040 Table 15. REGISTER DEFINITION (continued) 16 bit Default Value Write Address (Hex) Hex/Dec SPI State Description 01D1 CC11h CONFIG Only Config1 01D9 0000h CONFIG or IDLE Config2 01E1 000Ah CONFIG or IDLE Analog/Digital Power Mode 01E9 0000h CONFIG or IDLE Dual-Video Repetition 01F1 CONFIG or IDLE...
  • Page 27 KAC−12040 Table 15. REGISTER DEFINITION (continued) 16 bit Default Value Write Address (Hex) Hex/Dec SPI State Description 4029 0000h CONFIG or IDLE OTP Write Data 4031 0000h CONFIG or IDLE Command_Done_FB 4041 0000h CONFIG or IDLE OTP Read Data 4061 0000h CONFIG or IDLE Soft Reset...

  • Page 28: Absolute Maximum Ratings

    KAC−12040 ABSOLUTE MAXIMUM RATINGS For Supplies and Inputs the maximum rating is defined as degraded and may be damaged. Operation at these values a level or condition that should not be exceeded at any time. will reduce Mean Time to Failure (MTTF). If the level or the condition is exceeded, the device will be Table 16.
  • Page 29 KAC−12040 OPERATING RATINGS Table 18. INPUT CLOCK CONDITIONS Parameter Minimum Typical Maximum Unit Frequency for Clk_In1 and Clk_In2 Duty Cycle for Clk_In1 and Clk_In2 RESETN − − TRIGGER Pin Minimum Pulse Width − − TRIGGER must be active at least 4 periods of PLL1 (~12.5 ns at 320 MHz) to start a capture cycle. The polarity of the active level is configurable by SPI (Register 01D8h Bit 0), the default is active high (i.e.
  • Page 30 KAC−12040 Table 21. SUPPLIES Parameter Symbol Minimum Typical Maximum Unit LVDS IO Supply VDD_LVDS 3.15 3.30 3.63 Pixel High Voltage Supply AVDD_HV 3.40 3.50 3.60 Pixel Low Voltage Supply Vref_P 2.71 2.80 2.88 Analog Power Supply AVDD_LV 1.71 1.80 1.89 Digital Power Supply VDD_DIG 1.90...
  • Page 31 KAC−12040 SPI (SERIAL PERIPHERAL INTERFACE) The SPI communication interface lets the application an embedded slave SPI interface. The application system is system to control and configure the sensor. The sensor has the master of the SPI bus. Table 22. Sensor I/O Direction Name Description...
  • Page 32 KAC−12040 SPI Protocol Byte 0 Byte 1 Byte 2 Byte 3 8 Cycles 8 Cycles 8 Cycles 8 Cycles Sclk 16 Bit 16 Bit MOSI Address Word Data to Write Figure 23. SPI Write Byte Order Byte 0 Byte 1 Byte 2 Byte 3 8 Cycles...
  • Page 33 KAC−12040 SPI Interface … CS_HOLD CS_SETUP CYCLE … SETUP HOLD MOSI OUT_DELAY OUT_DELAY_CSN MISO MSB−1 Figure 25. SPI Timing Chronogram Table 24. SPI TIMING SPECIFICATION Symbol Minimum Value Maximum Value Unit CYCLE − SETUP − HOLD − CS_SETUP − CS_HOLD OUT_DELAY_CSN OUT_DELAY www.onsemi.com...

  • Page 34: Lvds Interface

    KAC−12040 LVDS INTERFACE RL = 100 W ±1%, Typical values are at VDD_LVDS = The data output can be configured to follow standard TIA/EIA−644−A LVDS specification or a low power mode 3.3 V. compatible with common Sub-LVDS definition used in Use register 2449h to select standard or Sub-LVDS.
  • Page 35 KAC−12040 In-Block LVDS Timing Specification The tables below give LVDS timing specifications for no data de-skew applied and with data de-skewing applied. Ideal Sample Times = Center of Data Data Clock Figure 26. LVDS Timing Chronogram Table 28. IN-BLOCK LVDS TIMING SPECIFICATION (Data Transition Uncertainty −...

  • Page 36: Storage And Handling

    KAC−12040 STORAGE AND HANDLING Table 31. STORAGE CONDITIONS Description Symbol Minimum Maximum Unit Notes °C Storage Temperature −40 Humidity 1. Long-term storage toward the maximum temperature will accelerate color filter degradation. 2. T = 25°C. Excessive humidity will degrade MTTF. For information on ESD and cover glass care and For quality and reliability information, please download cleanliness, please download the Image Sensor Handling...

  • Page 37: Mechanical Information

    KAC−12040 MECHANICAL INFORMATION Completed Assembly Notes: 1. See Ordering Information for marking code. 2. No materials to interfere with clearance through package holes. 3. Imaging Array is centered at the package center. 4. Length dimensions in mm units. Figure 27. Completed Assembly (1 of 5) www.onsemi.com...
  • Page 38 KAC−12040 Figure 28. Completed Assembly (2 of 5) www.onsemi.com...
  • Page 39 KAC−12040 Figure 29. Completed Assembly (3 of 5) www.onsemi.com...
  • Page 40 KAC−12040 Figure 30. Completed Assembly (4 of 5) Figure 31. Completed Assembly (5 of 5) www.onsemi.com...
  • Page 41 PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800−282−9855 Toll Free ON Semiconductor Website: www.onsemi.com Literature Distribution Center for ON Semiconductor USA/Canada Order Literature: http://www.onsemi.com/orderlit 19521 E. 32nd Pkwy, Aurora, Colorado 80011 USA Europe, Middle East and Africa Technical Support: Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada...
  • Page 42 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: ON Semiconductor KAC-12040-ABA-JD-AA KAC-12040-CBA-JD-AA KAC-12040-CBA-JD-BA KAC-12040-ABA-JD-BA...

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